E-STE100P View Datasheet(PDF) - STMicroelectronics
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E-STE100P Datasheet PDF : 31 Pages
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STE100P
Table 2. Pin Description (continued)
Pin No. Name
Type
Description
15
iref
O
Reference Resistor connecting pin for reference current, directly connect a 5KΩ ±
1% resistor to Vss.
38
ledr10
I/O LED display for 10Ms/s link status. This pin will be driven on continually when
10Mb/s network operating speed is detected.
The pull-up/pull-down status of this pin is latched into the PR20 bit 7 during
power up/reset.
37
ledtr
LED display for Tx/Rx Activity status. This pin will be driven on at a 10 Hz blinking
frequency when either effective receiving or transmitting is detected.
The status of this pin is latched into the PR20 bit 6 during power up/reset.
36
ledl
I/O LED display for Link Status. Blinks when there is TX or RX activity. This pin will be
driven on continually when a good Link test is detected.
The status of this pin is latched into the PR20 bit 5 during power up/reset.
35
ledc
I/O LED display for Full Duplex or Collision status. This pin will be driven on
continually when a full duplex configuration is detected. This pin will be driven on
at a 20 Hz blinking frequency when a collision status is detected in the half duplex
configuration.
The status of this pin is latched into the PR20 bit 4 during power up/reset.
34
leds
I/O LED display for 100Ms/s link status. This pin will be driven on continually when
100Mb/s network operating speed is detected.
The status of this pin is latched into the PR20 bit 3 during power up/reset.
64
cfg0
I
Configuration Control 0.
When A/N is enabled, cfg0 determines operating mode advertisement
capabilities in combination with cfg1 when mf0/ PR0:12 =1. (See Table 2)
When A/N is disabled, cfg1 disables mlt3 and directly affects PR19:0
When cfg0 is Low, mlt3 encoder/decoder is enabled and PR19:1 =0.
When cfg0 is High, mlt3 encoder/decoder is bypassed and PR19:1 = 1.
63
cfg1
I
Configuration Control 1.
When A/N is enabled, cfg1 determines operating mode advertisement
capabilities in combination with cfg1 when mf0/ PR0:12 =1. (See Table 2)
When A/N is disabled, CFG1 enables Loopback mode and directly affects PR0
bit 14.
When cfg1 is Low, Loopback mode is disabled and PR0:14 = 0.
When cfg1 is High, Loopback mode is enabled and PR0:14 = 1.
28
reset
I
Reset (Active-Low). This input must be held low for a minimum of 1 ms to reset
the STE100P. During Power-up, the STE100P will be reset regardless of the state
of this pin, and this reset will not be complete until after >1ms.
29
rip
O
Reset In Progress. This output is used to indicate when the device has
completed power-up/reset and the registers and functions can be accessed.
When rip is High, power-up/reset has been successful and the device can be
used normally
When rip is Low, device reset is not complete.
8, 30,31,
nc
32
nc (No Connection)
26, 33
test,
test_se
Test pins. Should be tied to ground for normal operation
27
pwrdwn
I
Power Down. When High, forces STE100P into Power Down mode. This pin is
OR’ed with the Power Down bit (PR0:11). During the Power Down mode, txp/txn
outputs and all LED outputs are 3-stated, and the MII interface is isolated.
5/31
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