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E-STE100P View Datasheet(PDF) - STMicroelectronics

Part Name
Description
View to exact match
E-STE100P
ST-Microelectronics
STMicroelectronics ST-Microelectronics
E-STE100P Datasheet PDF : 31 Pages
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3 PIN ASSIGNMENT DIAGRAM
Figure 4. Pin Connection
STE100P
mf4
mf3
mf2
mf1
mf0
fde
gnda
nc
vcca
gnda
x2
x1
vcca
gnda
iref
vcca
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
rx_dv
rxd0
rxd1
vcce/i
rdx2
rdx3
mdc
mdio
gnde/i
vcce/i
ledr10
ledtr
ledl
ledc
leds
test_se
D99TL457B
4 PIN DESCRIPTION
Table 2. Pin Description
Pin No. Name
Type
Description
MII Data Interface
52
txd4
58
txd3
57
txd2
56
txd1
55
txd0
I
Transmit Data. The Media Access Controller (MAC) drives data to the STE100P
using these inputs.
txd4 is monitored only in Symbol (5B) Mode.
These signals must be synchronized to the tx_clk.
54
tx_en
I
Transmit Enable. The MAC asserts this signal when it drives valid data on the
txd inputs. This signal must be synchronized to the tx_clk.
53
tx_clk
I/O Transmit Clock. Normally the STE100P drives tx_clk. Refer to the Clock
Requirements discussion in the Functional Description section.
25 MHz for 100 Mbps operation.
2.5 MHz for 10 Mbps operation.
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