SMD1102P View Datasheet(PDF) - Summit Microelectronics

Part Name

Description

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SMD1102P

10-Bit Data Acquisition System for Autonomous Environmental Monitoring

Summit Microelectronics 

SMD1102 / 1103 / 1113

Start and Stop Conditions

Both Data and Clock lines remain high when the bus is not

busy. Data transfer between devices may be initiated with

a Start condition only when SCL and SDA are high. A high-

to-low transition of the Data line while the Clock line is high

is defined as a Start condition. A low-to-high transition of

the Data line while the Clock line is high is defined as a Stop

condition. See Figure 12.

START

Condition

STOP

Condition

SCL

SDA In

2033 Fig10

Figure 12. Start and Stop Conditions

SCL

1

2

3

8

9

SDA

Trans

SDA

Rec

ACK

2033 Fig11

Figure 13. Acknowledge Timing

Protocol

The protocol defines any device that sends data onto the

bus as a Transmitter, and any device that receives data as

a Receiver. The device controlling data transmission is

called the Master, and the controlled device is called the

Slave. In all cases the Summit Microelectronic devices

are slave devices, since they never initiate any data

transfers.

Acknowledge

Data is always transferred in 8-Bit bytes. Acknowledge

(ACK) is used to indicate a successful data transfer. The

Transmitting device will release the bus after transmitting

eight bits. During the ninth clock cycle the Receiver will

pull the SDA line low to Acknowledge that it received the

eight bits of data (See Figure 13). The termination of a

Master Read sequence is indicated by a non-Acknowl-

edge (NACK), where the Master will leave the Data line

high.

In the case of a Read from a Summit part, when the last

byte has been transferred to the Master, the Master will

leave the Data line high for a NACK. This will cause the

Summit part to stop sending data, and the Master will issue

a Stop on the clock pulse following the NACK.

In the case of a Write to a Summit part the Master will send

a Stop on the clock pulse after the last Acknowledge. This

will indicate to the Summit part that it should begin its

internal nonvolatile write cycle.

Read and Write

The first byte from a Master is always made up of the eight

bits illustrated in Table 1.

In the read mode the SMD1102/1103/1113 transmits eight

bits of data, then releases the SDA line, and monitors the

line for an Acknowledge signal. If an Acknowledge is

detected, and no STOP condition is generated by the

Master, the device will continue to transmit data. If an

Acknowledge is not detected (NACK), the device will

terminate further data transmission.

In the write mode the SMD1102/1103/1113 receives eight

bits of data, then generates an Acknowledge signal. It will

continue to generate ACKs until a STOP condition is

generated by the Master.

SUMMIT MICROELECTRONICS, Inc.

2033 8.1 10/04/01

11

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