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CAT24C018JA-1.8TE13 View Datasheet(PDF) - Catalyst Semiconductor => Onsemi

Part Name
Description
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CAT24C018JA-1.8TE13
Catalyst
Catalyst Semiconductor => Onsemi Catalyst
CAT24C018JA-1.8TE13 Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
CAT24C01B
FUNCTIONAL DESCRIPTION
The CAT24C01B uses a 2-wire data transmission pro-
tocol. The protocol defines any device that sends data to
the bus to be a transmitter and any device receiving data
to be a receiver. Data transfer is controlled by the Master
device which generates the serial clock and all START
and STOP conditions for bus access. The CAT24C01B
operates as a Slave device. Both the Master and Slave
devices can operate as either transmitter or receiver, but
the Master device controls which mode is activated.
PIN DESCRIPTIONS
SCL: Serial Clock
The CAT24C01B serial clock input pin is used to clock
all data transfers into or out of the device. This is an input
pin.
SDA: Serial Data/Address
The CAT24C01B bidirectional serial data/address pin is
used to transfer data into and out of the device. The SDA
pin is an open drain output and can be wired with other
open drain or open collector outputs.
2-WIRE BUS PROTOCOL
The following defines the features of the 2-wire bus
protocol:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
Figure 1. Bus Timing tF
SCL
tSU:STA
SDA IN
SDA OUT
tHIGH
tR
tLOW
tLOW
tHD:DAT
tHD:STA
tSU:DAT
tAA
tDH
Figure 2. Write Cycle Timing
SCL
tSU:STO
tBUF
5020 FHD F03
SDA
8TH BIT
BYTE n
ACK
Figure 3. Start/Stop Timing
Doc. No. 1081, Rev. B
SDA
SCL
START BIT
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
5020 FHD F04
STOP BIT
5020 FHD F05
4
 

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