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5962R0922503V9A View Datasheet(PDF) - Intersil

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5962R0922503V9A Datasheet PDF : 25 Pages
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ISL70001ASEH
Functional Description
The ISL70001ASEH is a monolithic, fixed frequency, current-
mode synchronous buck regulator with user configurable power
blocks. Two ISL70001ASEH devices can be used to provide a
total DC/DC solution for FPGAs, CPLDs, DSPs and CPUs.
The ISL70001ASEH utilizes peak current-mode control with
integrated compensation and switches at a fixed frequency of
1MHz. Two ISL70001ASEH devices can be synchronized 180°
out-of-phase to reduce input RMS ripple current. These attributes
reduce the number and size of external components required,
while providing excellent output transient response. The
internal synchronous power switches are optimized for high
efficiency and good thermal performance.
The chip features a comparator type enable input that provides
flexibility. It can be used for simple digital on/off control or,
alternately, can provide undervoltage lockout capability by
using two external resistors to precisely sense the level of an
external supply voltage. A power-good signal indicates when the
output voltage is within ±11% typical of the nominal output
voltage.
Regulator start-up is controlled by an analog soft-start circuit,
which can be adjusted from approximately 2ms to 200ms by
using an external capacitor.
The ISL70001ASEH differs from the ISL70001SEH in the fault
counts needed to initiate an overcurrent or undervoltage
condition. The ISL70001ASEH also has a lower standby supply
current.
Power Blocks
The power output stage of the regulator consists of six 1A
capable power blocks that are paralleled to provide full 6A
output current capability. The block diagram in Figure 21 shows a
top level view of the individual power blocks.
PVIN1
LX1
PGND1
PVIN2
LX2
PGND2
PVIN3
LX3
PGND3
POWER BLOCK 1
POWER BLOCK 6
POWER BLOCK 2
POWER BLOCK 5
POWER BLOCK 3
POWER BLOCK 4
PVIN6
LX6
PGND6
PVIN5
LX5
PGND5
PVIN4
LX4
PGND4
FIGURE 21. POWER BLOCK DIAGRAM
Each power block has a power supply input pin, PVINx, a phase
output pin, LXx, and a power supply ground pin, PGNDx. All PVINx
pins must be connected to a common power supply rail and all
PGNDx pins must be connected to a common ground. LXx pins
should be connected to the output inductor based on the
required load current, but must include the LX4 pin. For example,
if 3A of output current is needed, any three LXx pins can be
connected to the inductor as long as one of them is the LX4 pin.
The unused LXx pins should be left unconnected. Connecting all
six LXx pins to the output inductor provides a maximum 6A of
output current. See the “Typical Application Schematic” on
page 5 for pin connection guidance.
A scaled pilot device associated with each power block provides
current feedback. Power block 4 contains the master pilot device
and this is why it must be connected to the output inductor.
Main Control Loop
During normal operation, the internal top power switch is turned
on at the beginning of each clock cycle. Current in the output
inductor ramps up until the current comparator trips and turns
off the top power MOSFET. The bottom power MOSFET turns on
and the inductor current ramps down for the rest of the cycle.
The current comparator compares the output current at the
ripple current peak to a current pilot. The error amplifier monitors
VOUT and compares it with an internal reference voltage. The
output voltage of the error amplifier drives a proportional current
to the pilot. If VOUT is low, the current level of the pilot is
increased and the trip off current level of the output is increased.
The increased output current raises VOUT until it is in agreement
with the reference voltage.
Output Voltage Selection
The output voltage of the ISL70001ASEH can be adjusted using
an external resistor divider as shown in Figure 22.
VREF = 0.6V
CREF = 220nF
RT = 1k
CC = 4.7nF
ERROR
AMPLIFIER
-
+ VREF
LXx LOUT
VOUT
COUT
RT CC
FB
REF
RB
CREF
FIGURE 22. OUTPUT VOLTAGE SELECTION
RT should be selected as 1kΩ to mitigate SEE. RT should be
shunted by a 4.7nF ceramic capacitor, CC, to mitigate SEE and to
improve loop stability margins. The REF pin should be bypassed
to AGND with a 220nF ceramic capacitor to mitigate SEE. It
should be noted that no current (sourcing or sinking) is available
from the REF pin. RB can be determined from Equation 3. The
designer can configure the output voltage from 0.8V to 85% of
the input voltage.
RB
=
RT
----------V----R---E----F----------
VOUT VREF
(EQ. 3)
Switching Frequency/Synchronization
The ISL70001ASEH features an internal oscillator running at a
fixed frequency of 1MHz ±15% over recommended operating
conditions. The regulator can be configured to run from the
internal oscillator or can be synchronized to another
ISL70001ASEH or an SEE hardened external clock with a
frequency range of 1MHz ±20%.
13
FN8365.0
May 22, 2013
 

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