GLT41116 View Datasheet(PDF) -
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GLT41116
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
May 1998 (Rev 2)
Truth Table: GLT41116
Function
Standby
Read: Word
RAS
H
L
CASL CASH WE
H→X H→X X
L
L
H
OE ADDRESS
DQs
X
High-Z
L ROW/COL Data Out
Notes
Read: Lower Byte
L
Read: Upper Byte
L
Write: Word(Early Write) L
L
H
H
L ROW/COL Lower Byte,Data-
Out
Upper Byte,High-Z
H
L
H
L ROW/COL Lower Byte,High-Z
Upper Byte,Data-
Out
L
L
L
X ROW/COL Data-In
Write: Lower Byte (Early) L
Write: Upper Byte (Early) L
Read Write
L
Fast-Page- 1st Cycle
L
Mode Read 2nd Cycle
L
L
H
L
X ROW/COL Lower Byte,Data-In
Upper Byte,High-Z
H
L
L
X ROW/COL Lower Byte,High-Z
Upper Byte,Data-In
L
L H→L L→H ROW/COL Data-Out,Data-In
1,2
H→L H→L H
L ROW/COL Data-Out
1
H→L H→L H
L
COL Data-Out
1
Fast-Page- 1st Cycle
L
H→L H→L L
X ROW/COL Data-In
2
Mode Write 2nd Cycle
L
H→L H→L L
X
COL Data-In
2
Fast-Page- 1st Cycle
L
H→L H→L H→L L→H ROW/COL Data-Out,Data-In
1,2
Mode Read-
1,2
Write
2nd Cycle
L
H→L H→L H→L L→H
COL Data-Out,Data-In
Hidden
Read
L→H→L L
L
H
L ROW/COL Data-Out
1
Refresh
Write
L→H→L L
L
L
X ROW/COL Data-In
2,3
RAS -Only Refresh
L
H
H
X
X
ROW High-Z
CBR Refresh
H→L
L
L
X
X
High-Z
4
Notes:
1. These READ cycles may also be BYTE READ cycles (either UCAS or LCAS active).
2. These WRITE cycles may also be BYTE READ cycles (either UCAS or LCAS active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active ( UCAS or LCAS ).
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
-4-
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
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