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IDT5V9885NLGI View Datasheet(PDF) - Integrated Device Technology

Part NameDescriptionManufacturer
IDT5V9885NLGI 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR IDT
Integrated Device Technology IDT
IDT5V9885NLGI Datasheet PDF : 37 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
IDT5V9885
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Name
PF32 NL28
Pin#
Pin#
I/O
Type
Description
CLKIN
1
1
I
LVTTL
Input Clock
XTALIN/REFIN
4
4
I
LVTTL
CRYSTAL_IN - Reference crystal input or external reference clock input
XTALOUT
5
5
O
LVTTL
CRYSTAL_OUT -Reference crystal feedback
GIN0/SDAT/TDI
19
16
I
LVTTL(3)
Multi-purpose inputs. Can be used for Frequency Control, SDAT(I2C), or TDI(JTAG).
GIN1/SCLK/TCK
20
17
I
LVTTL(3)
Multi-Purpose inputs. Can be used for Frequency Control, SCLK(I2C), or TCK(JTAG).
GIN2/TMS
24
21
I
LVTTL(3)
Multi-Purpose inputs. Can be used for Frequency Control or TMS (JTAG)
GIN3/SUSPEND
27
23
I
LVTTL(3)
Multi-Purpose inputs. Can be used for Frequency Control or as a suspend mode control
input (active HIGH).
GIN4/TRST
25
22
I
LVTTL(3)
Multi-Purpose inputs. Can be used for Frequency Control or TRST (JTAG)
GIN5/CLK_SEL
21
18
I
LVTTL(3)
Multi-Purpose inputs. Can be used for Frequency Control or input clock selector.
SHUTDOWN/OE
28
24
I
LVTTL(3)
Enables/disables the outputs or powers down the chip. The SP bit (0x1C) controls the
polarity of the signal to be either active HIGH or LOW. (Default is active HIGH.)
I2C/JTAG
22
19
I
3-level(2)
I2C (HIGH) or MFC Mode (MID) or JTAG Programming (LOW)
OUT1
6
6
O
LVTTL
Configurable clock output 1. Can also be used to buffer the reference clock.
OUT2
29
25
O
LVTTL
Configurable clock output 2
OUT3
8
7
O
LVTTL
Configurable clock output 3
OUT4
10
8
O
Adjustable(1) Configurableclockoutput4,Single-EndedorDifferentialwhencombinedwithOUT4
OUT4
11
9
O
Adjustable(1) Configurable complementary clock output 4, Single-Ended or Differential when
combined with OUT4
OUT5
15
13
O
Adjustable(1) Configurableclockoutput5,Single-EndedorDifferentialwhencombinedwithOUT5
OUT5
16
14
O
Adjustable(1) Configurable complementary clock output 5, Single-Ended or Differential when
combined with OUT5
OUT6
13
11
O
LVTTL
Configurable clock output 6
GOUT0/TDO/LOSS_LOCK 31
27
O
LVTTL(3)
Multi-Purpose Output. Can be programmed to use as PLL LOCK signal, LOSS_LOCK
or TDO in JTAG mode
GOUT1/LOSS_CLKIN
3
3
O
LVTTL
Multi-Purpose Output. Can be programmed to use as LOSS_CLKIN
VDD
7,12,17, 10,15,20
23,26,32 28
3.3V Power Supply
GND
2,9,14, 2,12,26
18,30
Ground
NOTES:
1. Outputs are user programmable to drive single-ended 3.3V LVTTL, differential LVDS, or differential LVPECL interface levels.
2. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are internally biased to VDD/2. They are not hot-insertable or over voltage tolerant.
3. The JTAG (TDO, TMS, TCLK, TRST, and TDI) and I2C (SCLK and SDAT) signals share the same pins with GIN signals.
4
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