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IDT5V9885NLGI View Datasheet(PDF) - Integrated Device Technology

Part NameDescriptionManufacturer
IDT5V9885NLGI 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR IDT
Integrated Device Technology IDT
IDT5V9885NLGI Datasheet PDF : 37 Pages
First Prev 31 32 33 34 35 36 37
IDT5V9885
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
RAM (PROGRAMMING REGISTER) TABLES
BIT #
(Default Settings)
Default
ADDR 7 6 5 4 3 2 1 0 Register
7
Hex Value
0x60 0 0 0 0 0 0 0 0
00
0x61 0 0 0 0 0 0 0 0
00
DITH0
0x62 0 0 0 0 0 0 0 0
00
0x63 0 0 0 0 0 0 0 0
00
0x64 0 0 0 0 0 0 0 0
00
0x65 0 0 0 0 0 0 0 0
00
0x66 0 0 0 0 0 0 0 0
00
0x67 0 0 0 0 0 0 0 0
00
0x68 0 0 0 0 0 0 0 0
00
0x69 0 0 0 0 0 0 0 0
00
DITH1
0x6A 0 0 0 0 0 0 0 0
00
0x6B 0 0 0 0 0 0 0 0
00
0x6C 0 0 0 0 0 0 0 0
00
0x6D 0 0 0 0 0 0 0 0
00
0x6E 0 0 0 0 0 0 0 0
00
0x6F 0 0 0 0 0 0 0 0
00
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
0x80
0x81
6
5
TSSC0[3:0]
X2_0
SD0[3:0][1]
SD0[3:0][3]
SD0[3:0][5]
SD0[3:0][7]
SD0[3:0][9]
SD0[3:0][11]
TSSC1[3:0]
X2_1
SD1[3:0][1]
SD1[3:0][3]
SD1[3:0][5]
SD1[3:0][7]
SD1[3:0][9]
SD1[3:0][11]
BIT #
4
3
2
1
NSSC0[3:0]
SS_OFFSET0[5:0]
SD0[3:0][0]
SD0[3:0][2]
SD0[3:0][4]
SD0[3:0][6]
SD0[3:0][8]
SD0[3:0][10]
NSSC1[3:0]
SS_OFFSET1[5:0]
SD1[3:0][0]
SD1[3:0][2]
SD1[3:0][4]
SD1[3:0][6]
SD1[3:0][8]
SD1[3:0][10]
CERR
0
DESCRIPTION
SPREAD SPRECTRUM SETTINGS FOR PLL0
SS_OFFSET0=SS Fractional Offset/ First Sample (Unsigned);
TSSC0=# of PFD Cycles Per SS Cycle Step, TSSC="0000" for SSC off (Default);
NSSC0=# of SS Samples to Use from SS Memory (Default is "0");
DITH0=LSB DITHER on Σ, ("1"=dither on, "0"=off (Default));
X2_0=ΣΔ output x2, ("1"=x2, "0"=normal (Default));
SD0=Delta-encoded samples (unsigned); Waveform start with SS_OFFSET0, then SS_OFFSET0+SD0[0], etc. (Default is "0");
SPREAD SPRECTRUM SETTINGS FOR PLL1
SS_OFFSET1=SS Fractional Offset/ First Sample (Unsigned);
TSSC1=# of PFD Cycles Per SS Cycle Step, TSSC="0000" for SSC off (Default);
NSSC1=# of SS Samples to Use from SS Memory (Default is "0");
DITH1=LSB DITHER on ΣΔ, ("1"=dither on, "0"=off (Default));
X2_1=ΣΔ output x2, ("1"=x2, "0"=off (Default));
SD1=Delta-encoded samples (unsigned); Waveform start with SS_OFFSET1, then SS_OFFSET1+SD1[0], etc. (Default is "0");
Read-Only
No Register Exists
CRC error in EEPROM
CERR = CRC error bit indicator ("1`" = CRC error)
Read-Only
35
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