datasheetbank_Logo    Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site
Part Name :

IDT5V9885NLGI View Datasheet(PDF) - Integrated Device Technology

Part NameIDT5V9885NLGI IDT
Integrated Device Technology IDT
Description3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
IDT5V9885NLGI Datasheet PDF : 37 Pages
First Prev 21 22 23 24 25 26 27 28 29 30 Next Last
IDT5V9885
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
I2C BUS DC CHARACTERISTICS
Symbol
VIH
VIL
VHYS
IIN
VOL
Parameter
Input HIGH Level
Input LOW Level
Hysteresis of Inputs
Input Leakage Current
Output LOW Voltage
Conditions
IOL = 3 mA
INDUSTRIAL TEMPERATURE RANGE
Min
Typ
Max
Unit
0.7 * VDD
V
0.3 * VDD
V
0.05 * VDD
V
±1.0
μA
0.4
V
I2C BUS AC CHARACTERISTICS FOR STANDARD MODE
Symbol Parameter
Min
Typ
Max
Unit
FSCLK
Serial Clock Frequency (SCLK)
0
100
KHz
tBUF
Bus free time between STOP and START
4.7
μs
tSU:START
tHD:START
Setup Time, START
Hold Time, START
4.7
μs
4
μs
tSU:DATA
Setup Time, data input (SDAT)
250
ns
tHD:DATA
Hold Time, data input (SDAT)(1)
0
μs
tOVD
Output data valid from clock
CB
Capacitive Load for Each Bus Line
tR
Rise Time, data and clock (SDAT, SCLK)
3.45
μs
400
pF
1000
ns
tF
Fall Time, data and clock (SDAT, SCLK)
300
ns
tHIGH
HIGH Time, clock (SCLK)
4
μs
tLOW
LOW Time, clock (SCLK)
4.7
μs
tSU:STOP
Setup Time, STOP
4
μs
NOTE:
1. A device must internally provide a hold time of at least 300ns for the SDAT signal (referred to the VIHMIN of the SCLK signal) to bridge the undefined region of the falling edge
of SCLK.
I2C BUS AC CHARACTERISTICS FOR FAST MODE
Symbol Parameter
Min
Typ
Max
Unit
FSCLK
Serial Clock Frequency (SCLK)
0
400
KHz
tBUF
Bus free time between STOP and START
1.3
μs
tSU:START Setup Time, START
0.6
μs
tHD:START Hold Time, START
0.6
μs
tSU:DATA
Setup Time, data input (SDAT)
100
ns
tHD:DATA
Hold Time, data input (SDAT)(1)
0
μs
tOVD
Output data valid from clock
CB
Capacitive Load for Each Bus Line
tR
Rise Time, data and clock (SDAT, SCLK)
20 + 0.1 * CB
0.9
μs
400
pF
300
ns
tF
Fall Time, data and clock (SDAT, SCLK)
20 + 0.1 * CB
300
ns
tHIGH
HIGH Time, clock (SCLK)
0.6
μs
tLOW
LOW Time, clock (SCLK)
1.3
μs
tSU:STOP
Setup Time, STOP
0.6
μs
NOTE:
1. A device must internally provide a hold time of at least 300ns for the SDAT signal (referred to the VIHMIN of the SCLK signal) to bridge the undefined region of the falling edge
of SCLK.
26
Direct download click here
 

DESCRIPTION:
The IDT5V9885 is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are three internal PLLs, each individually programmable, allowing for three unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. A glitchless automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation.
The IDT5V9885 can be programmed through the use of the I2C or JTAG interfaces. The programming interface enables the device to be programmed when it is in normal operation or what is commonly known as in system programmable. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. JTAG boundary scan is also implemented.

FEATURES:
• Three internal PLLs
• Internal non-volatile EEPROM
• JTAG and FAST mode I2C serial interfaces
• Input Frequency Ranges: 1MHz to 400MHz
• Output Frequency Ranges: 4.9kHz to 500MHz
• Reference Crystal Input with programmable oscillator gain and programmable linear load capacitance
   − Crystal Frequency Range: 8MHz to 50MHz
• Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider
• 10-bit post-divider blocks
• Fractional Dividers
• Two of the PLLs support Spread Spectrum Generation capability
• I/O Standards:
   − Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS
   − Inputs - 3.3V LVTTL/ LVCMOS
• Programmable Slew Rate Control
• Programmable Loop Bandwidth Settings
• Programmable output inversion to reduce bimodal jitter
• Redundant clock inputs with glitchless auto and manual switchover options
• JTAG Boundary Scan
• Individual output enable/disable
• Power-down mode
• 3.3V VDD
• Available in TQFP and VFQFPN packages

 

Share Link : IDT
@ 2014 - 2018  [ Home ] [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]