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IDT5V9885NLGI View Datasheet(PDF) - Integrated Device Technology

Part NameIDT5V9885NLGI IDT
Integrated Device Technology IDT
Description3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
IDT5V9885NLGI Datasheet PDF : 37 Pages
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IDT5V9885
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
EXTERNAL I2C INTERFACE CONDITION
KEY:
INDUSTRIAL TEMPERATURE RANGE
From Master to Slave
111222333444 From Master to Slave, but can be omitted if followed by the correct sequence
Normally data transfer is terminated by a STOP condition generated by the Master. However, if the Master still wishes to communicate on the bus, it can
generate a repeated START condition, and address another Slave address without first generating a STOP condition.
From Slave to Master
SYMBOLS:
ACK - Acknowledge (SDA LOW)
NACK - Not Acknowledge (SDA HIGH)
Sr - Repeated Start Condition
S - START Condition
P - STOP Condition
PROGWRITE
S Address R/W ACK Command Code ACK Register ACK Data ACK P
7-bits 0 1-bit 8-bits: xxxxxx00 1-bit 8-bits 1-bit 8-bits 1-bit
Figure 3: Progwrite Command Frame
Writes can continue as long as a Stop condition is not sent and each byte will increment the register address.
PROGREAD
Note: If the expected read command is not from the next higher register to the previous read or write command, then set a known "read" register address
prior to a read operation by issuing the following command:
S Address R/W ACK Command Code ACK Register ACK P
7-bits 0 1-bit 8-bits: xxxxxx00 1-bit 8-bits 1-bit
Figure 4a: Prior to Progread Command Set Register Address
The user can ignore the STOP condition above and use a repeated START condition instead, straight after the slave acknowledgement bit (i.e., followed by
the Progread command):
Sr Address R/W ACK ID Byte ACK Data_1 ACK Data_2 ACK Data_last NACK P
7-bits 1 1-bit 8 bits 1-bit 8-bits 1-bit 8-bits 1-bit 8-bits 1-bit
Figure 4b: Progread Command Frame
Note: Figure 4b above by itself is the Progread command format. The ID byte for the 5V9885 is 10hex. Each byte recieved increments the register address.
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DESCRIPTION:
The IDT5V9885 is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are three internal PLLs, each individually programmable, allowing for three unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. A glitchless automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation.
The IDT5V9885 can be programmed through the use of the I2C or JTAG interfaces. The programming interface enables the device to be programmed when it is in normal operation or what is commonly known as in system programmable. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. JTAG boundary scan is also implemented.

FEATURES:
• Three internal PLLs
• Internal non-volatile EEPROM
• JTAG and FAST mode I2C serial interfaces
• Input Frequency Ranges: 1MHz to 400MHz
• Output Frequency Ranges: 4.9kHz to 500MHz
• Reference Crystal Input with programmable oscillator gain and programmable linear load capacitance
   − Crystal Frequency Range: 8MHz to 50MHz
• Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider
• 10-bit post-divider blocks
• Fractional Dividers
• Two of the PLLs support Spread Spectrum Generation capability
• I/O Standards:
   − Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS
   − Inputs - 3.3V LVTTL/ LVCMOS
• Programmable Slew Rate Control
• Programmable Loop Bandwidth Settings
• Programmable output inversion to reduce bimodal jitter
• Redundant clock inputs with glitchless auto and manual switchover options
• JTAG Boundary Scan
• Individual output enable/disable
• Power-down mode
• 3.3V VDD
• Available in TQFP and VFQFPN packages

 

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