|IDT5V9885NLGI||3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR|
Integrated Device Technology
|IDT5V9885NLGI Datasheet PDF : 37 Pages |
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
The input clock selection will switch to the secondary clock source when there are no transitions on the primary clock source for two secondary clock cycles.
LOSS_LOCK and LOSS_CLKIN signals will be asserted. LOSS_LOCK will remain asserted until the PLL achieves lock, as previously defined, to the new input
clock. If there are no transitions on both clock sources, the LOSS_LOCK signal and LOSS_CLKIN signal will be asserted. After a stable and valid primary clock
source is present for either 8 or 1024 primary clock cycles, the input clock selection will automatically switch back to the primary clock source and LOSS_CLKIN
signal will be deasserted. The CLK_SEL pin can be left floating in this auto-revertive mode. The OKC bit (0x1D) determines the number of valid primary clock
cycles of either 8 or 1024 before switching back to the primary clock source. If OKC is set to "0", the primary clock will be re-selected as the input clock if the
primary clock is present for 8 primary clock cycles. If OKC is set to "1", the re-select threshold is 1024 primary clock cycles. (Actual switchover times will vary.)
Note that both clock inputs must be at the same frequency in order for the auto-revertive switchover to function properly. If both reference clocks are at different
frequencies, the device will always remain on the primary clock unless it is absent for two secondary clock cycles.
In all switchover modes, LOSS_LOCK signal is asserted for at least two input clock cycles of the newly selected clock when switching clock sources (manually
CLOCK SWITCH MATRIX AND OUTPUTS
All three PLL outputs and the currently selected input clock source are routed into and through a clock matrix. The user is able to select which PLL output and
clock source is routed to which output bank via the SRCx bits (0x34, 0x35). Each output bank has its own set of SRC bits. Refer to the RAM table for more
information. Note that OUT1 will be based off the reference clock and the only output bank toggling under the default RAM bit settings.
Outputs 1, 2 and 3 are 3.3V LVTTL. Outputs banks 4 and 5 can be 3.3V LVTTL, LVPECL or LVDS. The LVDS and LVPECL selection is determined by
the LVLx bits (0x54, 0x58). Each output bank has individual slew-rate control (SLEWx bits). Each output can be individually inverted (INVx bits); when using
LVPECL or LVDS modes, one of the outputs in each LVPECL/LVDS pair should be inverted. All output banks except OUT1 have a programmable 10-bit post-
divider (Qx bits) with two selectable divide configurations via the ODIVx bits.
There are four settings for the programmable slew rate, 0.7V/ns, 1.25V/ns, 2V/ns, and 2.75V/ns; this only applies to the 3.3V LVTTL outputs. The differential
outputs are not slew rate programmable in LVPECL or LVDS modes. SLEW4 and/or SLEW5 must be set to 2.75V/ns for stable output operation . For LVTTL
output frequency rates higher than 100MHz, a slew rate of 2V/ns or greater should be selected. The post-dividers can be disabled using the PMx bit, which
is described in the PRE-SCALER, FEEDBACK-DIVIDER, AND POST-DIVIDER section. Each output can also be enabled/disabled, which is described in the
'SHUTDOWN/SUSPEND/ENABLE of OUTPUTS' section. Refer to the RAM table for all binary settings.
HIGH LEVEL BLOCK DIAGRAM FOR CONFIGURATION SCHEME
PLLs and Control
I 2C or JTAG
NOTE: Diagram does not represent actual number of die on chip.
|Direct download click here|
|Share Link :|