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IDT5V9885NLGI View Datasheet(PDF) - Integrated Device Technology

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IDT5V9885NLGI
IDT
Integrated Device Technology IDT
IDT5V9885NLGI Datasheet PDF : 37 Pages
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IDT5V9885
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
MODE2 - Manual Frequency Control (MFC) Mode for all PLLs
In this mode, the configuration of PLL0, PLL1, and PLL2 can be changed during operation. The GINx pins are used to control the selection of up to four different
Dx, Mx, P, RZx, CZx, CPx, and IPx configurations for each PLL. GIN0 and GIN1 become configuration selection pins for D0 and M0 of PLL0, GIN2 and GIN3
become configuration selection pins for D1 and M1 of PLL1, and GIN4 and GIN5 become configuration selection pins for D2 and M2 of PLL2. The output GOUT0
will become an indicator for loss of PLL lock (LOSS_LOCK). GOUT1 pin will become an indicator for loss of the selected clock (LOSS_CLKIN).
The output banks will have two different P configurations to choose from for each of the four PLL configurations. Each of the two P configurations has its own
set of PM bits (See the PRE-SCALERS, FEEDBACK-DIVIDERS, POST-DIVIDERS section for more detail on the PM bits). Use the ODIV bit to choose which
post-divider configuration to associate with a specific PLL configuration. For example, if ODIV2_CONFIG2=1, then when Config2 is selected Qx[9:0]_CONFIG1
is selected as the post-divider value to be used. Note that there is an ODIVx bit for each of the PLL configurations. In this way, the post-divider values can change
with the configuration.
To enter this mode, users must set MFC bit to "0", and I2C/JTAG pin must be left floating.
GIN1 Pin
0
0
1
1
GIN0 Pin
0
1
0
1
PLL0 Configuration Selection (Mode 2)
Configuration 0
Configuration 1
Configuration 2
Configuration 3
GIN5 Pin
0
0
1
1
GIN4 Pin
0
1
0
1
PLL2 Configuration Selection (Mode 2)
Configuration 0
Configuration 1
Configuration 2
Configuration 3
GIN3 Pin
0
0
1
1
GIN2 Pin
0
1
0
1
PLL1 Configuration Selection (Mode 2)
Configuration 0
Configuration 1
Configuration 2
Configuration 3
MODE3 - I2C Programming Mode
In this mode, GIN0, GIN1, GIN3 and GIN5 become SDAT (I2C data), SCLK (I2C clock), SUSPEND and CLK_SEL signal pins, respectively. The output GOUT0
will become an indicator for loss of PLL lock (LOSS_LOCK). GOUT1 pin will become an indicator for loss of the selected clock (LOSS_CLKIN). GIN2 and GIN4
are not available to users.
To enter this mode, I2C/JTAG pin must be set HIGH.
MODE4 - JTAG Programming Mode
In this mode, GIN0, GIN1, GIN2, GIN3, GIN4 and GIN5 will become TDI (JTAG data in), TCK (JTAG clock), TMS (JTAG control signal), SUSPEND, TRST
(JTAG reset) and CLK_SEL signal pins, respectively. The output GOUT0 will become JTAG TDO signal, and GOUT1 will be an indicator for loss of the selected
clock (LOSS_CLKIN).
To enter this mode, I2C/JTAG pin must be set LOW.
Multi-Purpose pins
GIN0
GIN1
GIN2
GIN3
GIN4
GIN5
GOUT0
GOUT1
Mode1
GIN0
GIN1
GIN2
SUSPEND
n/a
CLK_SEL
LOSS_LOCK
LOSS_CLKIN
Manual Frequency Control modes
Mode2
JTAG
GIN0
TDI
GIN1
TCK
GIN2
TMS
GIN3
SUSPEND
GIN4
TRST
GIN5(1)
CLK_SEL
LOSS_LOCK
TDO
LOSS_CLKIN
LOSS_CLKIN
NOTE:
1. The PLL(s) will lock onto the primary clock and the manual switchover can be controlled by the PRIMCLK bit.
I2C
SDAT
SCLK
n/a
SUSPEND
n/a
CLK_SEL
LOSS_LOCK
LOSS_CLKIN
15
 

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