datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

E-ETC5054D-X/HTR View Datasheet(PDF) - STMicroelectronics

Part Name
Description
View to exact match
E-ETC5054D-X/HTR
ST-Microelectronics
STMicroelectronics ST-Microelectronics
E-ETC5054D-X/HTR Datasheet PDF : 18 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ETC5054 - ETC5057
edges clock out the remaining seven bits. The DX
output is disabled by the falling BCLKX edge fol-
lowing the eighth rising edge, or by FSX going
low, which-ever comes later. A rising edge on the
receive frame sync pulse, FSR, will cause the
PCM data at DR to be latched in on the next eight
falling edges of BCLKR (BCLKX in synchronous
mode). Both devices may utilize the long frame
sync pulse in synchronous or asynchronous
mode.
TRANSMIT SECTION
The transmit section input is an operational ampli-
fier with provision for gain adjustment using two
external resistors, see figure 6. The low noise and
wide bandwidth allow gains in excess of 20 dB
across the audio passband to be realized. The op
amp drives a unitygain filter consisting of RD ac-
tive pre-filter, followed by an eighth order
switched-capacitor bandpass filter clocked at 256
kHz. The output of this filter directly drives the en-
coder sample-and-hold circuit. The A/D is of com-
panding type according to A-law (ETC5057) or µ
law (ETC5054) coding conventions. A precision
voltage reference is trimmed in manufacturing to
provide an input overload (tMAX) of nominally 2.5V
peak (see table of transmission characteristics).
The FSX frame sync pulse controls the sampling
of the filter output, and then the successive-ap-
proximation encoding cycle begins. The 8-bit
code is then loaded into a buffer and shifted out
through DX at the next FSX pulse. The total en-
coding delay will be approximately 165 µs (due to
the transmit filter) plus 125µs (due to encoding
delay), which totals 290µs. Any offset vol-tage
due to the filters or comparator is cancelled by
sign bit integration.
RECEIVE SECTION
The receive section consists of an expanding
DAC which drives a fifth order switched-capacitor
low pass filter clocked at 256 kHz. The decoder is
A-law (ETC5057) or µ–law (ETC5054) and the
5th order low pass filter corrects for the sin x/x at-
tenuation due to the 8 kHz sample and hold.
The filter is then followed by a 2nd order RC ac-
tive post-filter and power amplifier capable of driv-
ing a 600load to a level of 7.2 dBm. The re-
ceive section is unity-gain. Upon the occurence of
FSR, the data at the DR input is clocked in on the
falling edge of the next eight BCLKR (BCLKX) pe-
riods. At the end of the decoder time slot, the de-
coding cycle begins, and 10µs later the decoder
DAC output is updated. The total decoder delay
is 10µs (decoder update) plus 110µs (filter
delay) plus 62.5µs (1/2 frame), which gives ap-
proximately 180µs. A mute circuitry is a active
during 10ms when power up.
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VBB
VIN, VOUT
Toper
Tstg
Parameter
VCC to GNDA
VBB to GNDA
Voltage at any Analog Input or Output
Voltage at Any Digital Input or Output
Operating Temperature Range
Storage Temperature Range
Lead Temperature (soldering, 10 seconds)
Value
7
–7
VCC + 0.3 to VBB – 0.3
VCC + 0.3 to GNDA – 0.3
– 25 to + 125
– 65 to + 150
300
Unit
V
V
V
V
°C
°C
°C
ELECTRICAL OPERATING CHARACTERISTICS VCC = 5.0 V ± 5 %, VBB = – 5.0 V ± 5%GNDA = 0 V,
TA = 0 °C to 70 °C; Typical Characteristics Specified at VCC = 5.0 V, VBB = – 5.0 V, TA = 25 °C ; all signals
are referenced to GNDA.
Symbol
VIL
VIH
VOL
VOH
IIL
IIH
IOZ
Parameter
Input Low Voltage
Input High Voltage
Output Low Voltage
IL = 3.2mA
DX
IL = 3.2mA, Open Drain
TSX
Output High Voltage
IH = 3.2mA
DX
Input Low Current (GNDA VIN VIL, all digital inputs)
Input High Current (VIH VIN VCC) except BCLKR/BCLKSEL
Output Current in HIGH Impedance State (TRI-STATE)
(GNDA VO VCC)
DX
Min.
2.2
2.4
–10
–10
–10
Typ.
Max.
0.6
0.4
0.4
10
10
10
Unit
V
V
V
V
V
µA
µA
µA
5/18
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]