CY22150FC View Datasheet(PDF) - Cypress Semiconductor
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Description
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CY22150FC
Cypress Semiconductor
CY22150FC Datasheet PDF : 13 Pages
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CY22150
manufacturer), and the CapLoad setting during crystal
start-up.
Bits 3 and 4 of register 12H control the input crystal oscillator
gain setting. Bit 4 is the MSB of the setting, and bit 3 is the
LSB. The setting is programmed according to Table 2. All other
bits in the register are reserved and should be programmed as
shown in Table 3.
Using an External Clock as the Reference Input
The CY22150 can also accept an external clock as reference,
with speeds up to 133 MHz. With an external clock, the XDRV
(register 12H) bits must be set according to Table 4.
Table 1. Summary Table – CY22150 Programmable Registers
Register
Description
D7
D6
D5
D4
D3
D2
D1
D0
09H CLKOE control
0
0
CLK6
CLK5 LCLK4 LCLK3 LCLK2 LCLK1
OCH DIV1SRC mux and DIV1SRC DIV1N(6) DIV1N(5) DIV1N(4) DIV1N(3) DIV1N(2) DIV1N(1) DIV1N(0)
DIV1N divider
12H Input crystal oscillator
0
0
1
XDRV(1) XDRV(0)
0
0
0
drive control
13H Input load capacitor CapLoad CapLoad CapLoad CapLoad CapLoad CapLoad CapLoad CapLoad
control
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
40H Charge Pump and PB
1
41H counter
PB(7)
1
PB(6)
0
PB(5)
Pump(2) Pump(1) Pump(0)
PB(4)
PB(3)
PB(2)
PB(9)
PB(1)
PB(8)
PB(0)
42H PO counter, Q
counter
PO
Q(6)
Q(5)
Q(4)
Q(3)
Q(2)
Q(1)
Q(0)
44H Crosspoint switch
matrix control
CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1
for LCLK1 for LCLK1 for LCLK1 for LCLK2 for LCLK2 for LCLK2 for LCLK3 for LCLK3
45H
CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2
for LCLK3 for LCLK4 for LCLK4 for LCLK4 for CLK5 for CLK5 for CLK5 for CLK6
46H
CLKSRC1 CLKSRC0 1
1
1
1
1
1
for CLK6 for CLK6
47H DIV2SRC mux and DIV2SRC DIV2N(6) DIV2N(5) DIV2N(4) DIV2N(3) DIV2N(2) DIV2N(1) DIV2N(0)
DIV2N divider
Table 2. Programmable Crystal Input Oscillator Gain Settings
Crystal Input
Frequency
Cap Register Settings
Effective Load Capacitance
(CapLoad)
Crystal ESR
8 – 15 MHz
15 – 20 MHz
20 – 25 MHz
25 – 30 MHz
00H – 80H
6 pF to 12 pF
30Ω
60Ω
00
01
01
10
01
10
10
10
80H – C0H
12pF to 18pF
30Ω
60Ω
01
10
01
10
10
10
10
11
C0H – FFH
18pF to 30pF
30Ω
60Ω
01
10
10
10
10
11
11
N/A
Table 3. Bit Locations and Values
Address
D7
D6
D5
D4
D3
D2
D1
D0
12H
0
0
1
XDRV(1) XDRV(0)
0
0
0
Table 4. Programmable External Reference Input Oscillator Drive Settings
Reference Frequency
Drive Setting
1 – 25 MHz
00
25 – 50 MHz
01
50 – 90 MHz
10
90 – 133 MHz
11
Document #: 38-07104 Rev. *F
Page 4 of 13
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