CMX882 View Datasheet(PDF) - CML Microsystems Plc
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CMX882 Datasheet PDF : 70 Pages
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FRS Signalling Processor
CMX882
The following 5 registers (including 2 receive data registers) are read only
1.6.16 $B4 AUX ADC MONITOR DATA: 8-bit read-only
Bit:
7
6
5
4
3
2
1
0
Signal Monitor Data
This data holds the result of the last measurement performed by the auxiliary ADC. The signal processor
must be on to read Aux ADC data, so Power Down Control register b5 must be set to ‘1’. This is
independent of whether Tx or Rx modes are selected.
1.6.17
Bit:
$C6 STATUS: 16-bit read-only
15
14
13
12
In-band
XTCSS 4
IRQ
0
tone state
tone set
change
complete
11
CTCSS
state
change
10
DCS
state
change
9
8
Aux ADC
Aux ADC
Monitor High Monitor Low
Bit:
7
6
5
4
3
2
1
0
End of
FFSK data
FFSK data
transfer
required
Block
CRC error
Rx 2400b/s Rx 1200b/s
0
0
Programming
Flag
This word holds the current status of the CMX882: the value read out is only valid when bit 5 of the Power
Down Control register ($C0) is set to '1'. Changes in the Status register will cause the IRQ bit (bit 15) to
be set to '1' if the corresponding interrupt mask bit is enabled. An interrupt request is issued on the IRQN
pin when the IRQ bit is '1' and the IRQ MASK bit (bit 15 of register $CE) is set to '1'.
Bits 1 to 15 of the Status register are cleared to '0' after the Status register is read. Bit 0 is only cleared
by writing to the Programming Register.
Bits 14 and 2 to 1 are reserved.
Bits 13, 11 and 10 indicate that a In-band tone, CTCSS or DCS event caused the interrupt, the host
should then read the Tones Status register ($CC) for further information. In transmit these bits will be set
to '0'. Detection of the DCS turn off tone and removal of the DCS turn off tone are both flagged as DCS
events in the Status register, not as CTCSS events. The assertion or removal of the ‘XTCSS
Maintenance Tone’ (64.7Hz) is flagged as a CTCSS event.
In receive bit 12 indicates that a valid XTCSS 4 tone set with the correct addressing (see $C2) has been
detected, the 4 received tones are indicated in $C9. In Tx mode bit 12 will be set to '1' at the end of the
4th XTCSS tone transmitted.
Aux ADC High (bit 9) and Aux ADC Low (bit 8) reflect the recent history of the Aux ADC level, with
respect to the high and low thresholds. The most recent Aux ADC reading can be read from $B4.
Aux ADC
Monitor High
0
0
1
1
Aux ADC
Monitor Low
0
1
0
1
Aux ADC history since last reading:
Neither threshold crossed
Signal gone below low threshold
Signal gone above high threshold
Signal gone below low threshold and above high
threshold
In Rx mode bit 7 will be set at the same time as bit 6 after receiving the last part of a sized FFSK Frame
or Type 1 (frame head only) message, bit 5 (CRC) will also be updated at this time. When the host
detects bit 7 is set it may power down the CMX882 or set the CMX882 to transmit or receive new
information as appropriate.
2004 CML Microsystems Plc
47
D/882/7
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