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CMX882 View Datasheet(PDF) - CML Microsystems Plc

Part Name
Description
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CMX882
CML
CML Microsystems Plc CML
CMX882 Datasheet PDF : 70 Pages
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FRS Signalling Processor
CMX882
Table comparing different message types:
Data Block
Formatting
Type:
2
3
Total over-
air bits for
an 80 byte
message
720
1040
Air time for FFSK
message (ms)
at
at
1200b/s 2400b/s
600
300
867
433
4
1088
907
453
5
1088
907
453
Over air
efficienc
y
89%
62%
59%
59%
Burst length
protection at 1200b/s
[for 2400b/s divide
both times by 2]
None
<0.83ms in any
10ms
<0.83ms in any
10ms
<3.33ms in any
40ms
Probability
of detecting
errors
Zero
Poor
Excellent
Excellent
Higher levels of error protection have the penalty of adding extra bits to the over air signal and this
reduces the effective bit rate. Less error protection increases the effective bit rate, however in typical
radio conditions the penalty is a greater risk of errors leading to repeated messages and a net reduction
in effective bit rate compared to using error correction and detection.
1.5.5.5 Data Scrambling / Privacy Coding
It is preferable for MSK over air data to be reasonably random in nature to ensure the receiver can track
timing using the bit changes and to smooth the frequency spectrum. To reduce the possibility of User
Data causing long strings of 1’s or 0’s to be transmitted, a 16 bit data scrambler is provided and operates
on all bits after the Frame Head.
The default (standard) setting for this scrambler is with a start code (seed) of $FFFF and any receivers
with the same seed may decode this data. However, if the transmitter and receiver pre-arrange a
different seed then the scrambler will start its sequence in another place and any simple receiver that
does not know the transmitted seed will not be able to successfully decode the data. This method gives
over 65,000 different starting points and the chance of others decoding data successfully is reduced.
The CMX882 provides the option of two custom 16 bit words that are programmable by the user in
Program Register P0.2 to P0.5. Bits 0 and 1 in the Frame Head Format byte indicate which setting
(standard, Seed1, Seed2 or none) the flowing Data Block has been scrambled with, see section 1.6.11.
Note that a seed of $0000 will effectively turn off the scrambler and provide no protection against long
sequences of 1’s or 0’s. Reception of scrambled data will only be successful when the receiving device
has been programmed with the correct (identical) seed to that used by the transmitter.
By using this method the CMX882 provides a privacy code that will protect against casual monitoring,
however the data is not encrypted and a sophisticated receiver can decode the data by using moderately
simple decoding techniques. If data encryption is required it must be performed by the host. The
scrambler function is controlled by bits 0,1 of the Modem Control register ($C7).
1.5.5.6 Data Buffer Timing
Data must be transferred at the rate appropriate to the signal type and data format. The CMX882 buffers
signal data in up to two 16-bit registers. The CMX882 will issue interrupts to indicate when data is
available or required. The host must respond to these interrupts within the maximum allowable latency
for the signal type. Table 9 shows the maximum latencies for transferring signal data to maintain
appropriate data throughput.
2004 CML Microsystems Plc
31
D/882/7
 

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