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CAT24C03 View Datasheet(PDF) - Catalyst Semiconductor => Onsemi

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CAT24C03 Datasheet PDF : 18 Pages
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Figure 1. START/STOP Conditions
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. Slave Address Bits
1
0
1
0 A2 A1 A0 R/W CAT24C03
1
0
1
0 A2 A1 a8 R/W CAT24C05
CAT24C03/05
Figure 3. Acknowledge Timing
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER)
1
8
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (tAA)
BUS RELEASE DELAY (RECEIVER)
9
ACK SETUP (tSU:DAT)
Figure 4. Bus Timing
tF
SCL
tSU:STA
SDA IN
SDA OUT
tHIGH
tR
tLOW
tLOW
tHD:DAT
tHD:STA
tSU:DAT
tAA
tDH
tSU:STO
tBUF
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc No. 1116, Rev. B
 

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