|CAT22C10||256-Bit Nonvolatile CMOS Static RAM|
|CAT22C10 Datasheet PDF : 10 Pages |
At anytime, except during a store operation, taking the
RECALL pin low will initiate a recall operation. This is
independent of the state of CS, WE, or A0–A5. After the
RECALL pin has been held low for the duration of the
Recall Pulse Width (tRCP), the recall will continue inde-
pendent of any other inputs. During the recall, the entire
contents of the EEPROM array is transferred to the
Static RAM array. The first byte of data may be externally
accessed after the recalled data access time from end of
recall (tARC) is met. After this, any other byte may be
accessed by using the normal read mode.
If the RECALL pin is held low for the entire Recall Cycle
time (tRCC), the contents of the Static RAM may be
immediately accessed by using the normal read mode.
A recall operation can be performed an unlimited num-
ber of times without affecting the integrity of the data.
The outputs I/O0–I/O3 will go into the high impedance
state as long as the RECALL signal is held low.
At any time, except during a recall operation, taking the
STORE pin low will initiate a store operation. This takes
place independent of the state of CS, WE or A0–A5. The
STORE pin must be held low for the duration of the Store
Pulse Width (tSTP) to ensure that a store operation is
initiated. Once initiated, the STORE pin becomes a
“Don’t Care”, and the store operation will complete its
transfer of the entire contents of the Static RAM array
into the EEPROM array within the Store Cycle time
(tSTC). If a store operation is initiated during a write cycle,
the contents of the addressed Static RAM byte and its
corresponding byte in the EEPROM array will be un-
During the store operation, the outputs are in a high
impedance state. A minimum of 100,000 store opera-
tions can be performed reliably and the data written into
the EEPROM array has a minimum data retention time
of 10 years.
DATA PROTECTION DURING POWER-UP AND
The CAT22C10 has on-chip circuitry which will prevent
a store operation from occurring when VCC falls below
3.0V typ. This function eliminates the potential hazard of
spurious signals initiating a store operation when the
system power is below 3.0V typ.
Figure 4. Recall Cycle Timing
Figure 5. Store Cycle Timing
Doc. No. MD-1082, Rev. R
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice.
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