|CAT22C10||256-Bit Nonvolatile CMOS Static RAM|
|CAT22C10 Datasheet PDF : 10 Pages |
The configuration of the CAT22C10 allows a common
address bus to be directly connected to the address
inputs. Additionally, the Input/Output (I/O) pins can be
directly connected to a common I/O bus if the bus has
less than 1 TTL load and 100pF capacitance. If not, the
I/O path should be buffered.
When the chip select (CS) pin goes low, the device is
activated. When CS is forced high, the device goes into
the standby mode and consumes very little current. With
the nonvolatile functions inhibited, the device operates
like a Static RAM. The Write Enable (WE) pin selects a
write operation when WE is low and a read operation
when WE is high. In either of these modes, an array byte
(4 bits) can be addressed uniquely by using the address
lines (A0–A5), and that byte will be read or written to
through the Input/Output pins (I/O0–I/O3).
The nonvolatile functions are inhibited by holding the
STORE input and the RECALL input high. When the
RECALL input is taken low, it initiates a recall operation
which transfers the contents of the entire EEPROM
array into the Static RAM. When the STORE input is
taken low, it initiates a store operation which transfers
the entire Static RAM array contents into the EEPROM
The chip select (CS) input controls all of the functions of
the CAT22C10. When a high level is supplied to the CS
pin, the device goes into the standby mode where the
outputs are put into a high impendance state and the
power consumption is drastically reduced. With ISB less
than 100µA in standby mode, the designer has the
flexibility to use this part in battery operated systems.
When the chip is enabled (CS = low), the nonvolatile
functions are inhibited (STORE = high and RECALL =
high). With the Write Enable (WE) pin held high, the data
in the Static RAM array may be accessed by selecting an
address with input pins A0–A5. This will occur when the
outputs are connected to a bus which is loaded by no more
than 100pF and 1 TTL gate. If the loading is greater than
this, some additional buffering circuitry is recommended.
Figure 1. Read Cycle Timing
Doc. No. MD-1082, Rev. R
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice.
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