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CAT22C10 View Datasheet(PDF) - Catalyst Semiconductor => Onsemi

Part NameCAT22C10 Catalyst
Catalyst Semiconductor => Onsemi Catalyst
Description256-Bit Nonvolatile CMOS Static RAM
CAT22C10 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
The configuration of the CAT22C10 allows a common
address bus to be directly connected to the address
inputs. Additionally, the Input/Output (I/O) pins can be
directly connected to a common I/O bus if the bus has
less than 1 TTL load and 100pF capacitance. If not, the
I/O path should be buffered.
When the chip select (CS) pin goes low, the device is
activated. When CS is forced high, the device goes into
the standby mode and consumes very little current. With
the nonvolatile functions inhibited, the device operates
like a Static RAM. The Write Enable (WE) pin selects a
write operation when WE is low and a read operation
when WE is high. In either of these modes, an array byte
(4 bits) can be addressed uniquely by using the address
lines (A0–A5), and that byte will be read or written to
through the Input/Output pins (I/O0–I/O3).
The nonvolatile functions are inhibited by holding the
STORE input and the RECALL input high. When the
RECALL input is taken low, it initiates a recall operation
which transfers the contents of the entire E2PROM array
into the Static RAM. When the STORE input is taken low,
it initiates a store operation which transfers the entire
Static RAM array contents into the E2PROM array.
Standby Mode
The chip select (CS) input controls all of the functions of
the CAT22C10. When a high level is supplied to the CS
pin, the device goes into the standby mode where the
outputs are put into a high impendance state and the
power consumption is drastically reduced. With ISB less
than 100µA in standby mode, the designer has the
flexibility to use this part in battery operated systems.
When the chip is enabled (CS = low), the nonvolatile
functions are inhibited (STORE = high and RECALL =
high). With the Write Enable (WE) pin held high, the data
in the Static RAM array may be accessed by selecting an
address with input pins A0–A5. This will occur when the
outputs are connected to a bus which is loaded by no
more than 100pF and 1 TTL gate. If the loading is greater
than this, some additional buffering circuitry is recom-
Figure 1. Read Cycle Timing
5153 FHD F06
Doc. No. 25018-0A 2/98 N-1
Direct download click here

The CAT22C10 NVRAM is a 256-bit nonvolatile memory organized as 64 words x 4 bits. The high speed Static RAM array is bit for bit backed up by a nonvolatile E2PROM array which allows for easy transfer of data from RAM array to E2PROM (STORE) and from E2PROM to RAM (RECALL). STORE operations are completed in 10ms max. and RECALL operations typically within 1.5µs.

■ Single 5V Supply
■ Fast RAM Access Times:
■ Infinite E2PROM to RAM Recall
■ CMOS and TTL Compatible I/O
■ Power Up/Down Protection
■ 100,000 Program/Erase Cycles (E2PROM)
■ Low CMOS Power Consumption:
  –Active: 40mA Max.
  –Standby: 30 µA Max.
■ JEDEC Standard Pinouts:
  –18-pin DIP
  –16-pin SOIC
■ 10 Year Data Retention
■ Commercial, Industrial and Automotive Temperature Ranges

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