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ADSP-BF531 View Datasheet(PDF) - Analog Devices

Part Name
Description
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ADSP-BF531
ADI
Analog Devices ADI
ADSP-BF531 Datasheet PDF : 60 Pages
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ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Peripheral Interface (SPI) Port
—Master Timing
Table 26 and Figure 24 describe SPI port master operations.
Table 26. Serial Peripheral Interface (SPI) Port—Master Timing
VDDEXT = 1.8 V
LQFP/PBGA Packages
Parameter
Min
Max
Timing Requirements
tSSPIDM Data Input Valid to SCK Edge (Data Input Setup) 10.5
tHSPIDM SCK Sampling Edge to Data Input Invalid
–1.5
Switching Characteristics
tSDSCIM SPISELx Low to First SCK Edge
tSPICHM Serial Clock High Period
tSPICLM Serial Clock Low Period
tSPICLK Serial Clock Period
tHDSM Last SCK Edge to SPISELx High
tSPITDM Sequential Transfer Delay
tDDSPIDM SCK Edge to Data Out Valid (Data Out Delay)
tHDSPIDM SCK Edge to Data Out Invalid (Data Out Hold)
2tSCLK –1.5
2tSCLK – 1.5
2tSCLK – 1.5
4tSCLK – 1.5
2tSCLK – 1.5
2tSCLK – 1.5
0
–1.0
6
+4.0
VDDEXT = 1.8 V
MBGA Package
Min
Max
8.5
–1.5
2tSCLK –1.5
2tSCLK – 1.5
2tSCLK – 1.5
4tSCLK – 1.5
2tSCLK – 1.5
2tSCLK – 1.5
0
–1.0
6
+4.0
VDDEXT = 2.5 V/3.3 V
All Packages
Min
Max
Unit
7.5
ns
–1.5
ns
2tSCLK –1.5
2tSCLK – 1.5
2tSCLK – 1.5
4tSCLK – 1.5
2tSCLK – 1.5
2tSCLK – 1.5
0
–1.0
ns
ns
ns
ns
ns
ns
6
ns
+4.0 ns
SPISELx
(OUTPUT)
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
tSDSCIM
tSPICHM
tSPICLM
tSPICLM
tSPICHM
tDDSPIDM
MOSI
(OUTPUT)
MSB
CPHA = 1
MISO
(INPUT)
tSSPIDM
tHSPIDM
MSB VALID
tDDSPIDM
MOSI
(OUTPUT)
MSB
CPHA = 0
tSSPIDM
tHSPIDM
MISO
(INPUT)
MSB VALID
tSPICLK
tHDSM
tSPITDM
tHDSPIDM
LSB
tSSPIDM
tHSPIDM
LSB VALID
tHDSPIDM
LSB
LSB VALID
Figure 24. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. E | Page 37 of 60 | July 2007
 

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