AT49F001-55PI View Datasheet(PDF) - Atmel Corporation

Part Name

Description

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AT49F001-55PI

1-Megabit (128K x 8) 5-volt Only Flash Memory

Atmel Corporation 

AT49F001(N)(T)

Device Operation

READ: The AT49F001(N)(T) is accessed like an EPROM.

When CE and OE are low and WE is high, the data stored

at the memory location determined by the address pins is

asserted on the outputs. The outputs are put in the high

impedance state whenever CE or OE is high. This dual-line

control gives designers flexibility in preventing bus conten-

tion.

COMMAND SEQUENCES: When the device is first pow-

ered on it will be reset to the read or standby mode

depending upon the state of the control line inputs. In order

to perform other device functions, a series of command

sequences are entered into the device. The command

sequences are shown in the Command Definitions table.

The command sequences are written by applying a low

pulse on the WE or CE input with CE or WE low (respec-

tively) and OE high. The address is latched on the falling

edge of CE or WE, whichever occurs last. The data is

latched by the first rising edge of CE or WE. Standard

microprocessor write timings are used. The address loca-

tions used in the command sequences are not affected by

entering the command sequences.

RESET: A RESET input pin is provided to ease some sys-

tem applications. When RESET is at a logic high level, the

device is in its standard operating mode. A low level on the

RESET input halts the present device operation and puts

the outputs of the device in a high impedence state. If the

RESET pin makes a high to low transition during a program

or erase operation, the operation may not be sucessfully

completed and the operation will have to be repeated after

a high level is applied to the RESET pin. When a high level

is reasserted on the RESET pin, the device returns to the

read or standby mode, depending upon the state of the

control inputs. By applying a 12V ± 0.5V input signal to the

RESET pin, the boot block array can be reprogrammed

even if the boot block lockout feature has been enabled

(see Boot Block Programming Lockout Override section).

The RESET feature is not available for the AT49F001N(T).

ERASURE: Before a byte can be reprogrammed, the main

memory block or parameter block which contains the byte

must be erased. The erased state of the memory bits is a

logical “1”. The entire device can be erased at one time by

using a 6-byte software code. The software chip erase

code consists of 6-byte load commands to specific address

locations with a specific data pattern (please refer to the

Chip Erase Cycle Waveforms).

After the software chip erase has been initiated, the device

will internally time the erase operation so that no external

clocks are required. The maximum time needed to erase

the whole chip is tEC. If the boot block lockout feature has

been enabled, the data in the boot sector will not be

erased.

CHIP ERASE: If the boot block lockout has been enabled,

the Chip Erase function will erase Parameter Block 1,

Parameter Block 2, Main Memory Block 1, and Main Mem-

ory Block 2 but not the boot block. If the Boot Block Lockout

has not been enabled, the Chip Erase function will erase

the entire chip. After the full chip erase the device will

return back to read mode. Any command during chip erase

will be ignored.

SECTOR ERASE: As an alternative to a full chip erase, the

device is organized into sectors that can be individually

erased. There are two 8K-byte parameter block sections

and two main memory blocks. The 8K-byte parameter

block sections can be independently erased and repro-

grammed. The two main memory sections are designed to

be used as alternative memory sectors. That is, whenever

one of the blocks has been erased and reprogrammed, the

other block should be erased and reprogrammed before

the first block is again erased. The Sector Erase command

is a six bus cycle operation. The sector address is latched

on the falling WE edge of the sixth cycle while the 30H data

input command is latched at the rising edge of WE. The

sector erase starts after the rising edge of WE of the sixth

cycle. The erase operation is internally controlled; it will

automatically time to completion.

BYTE PROGRAMMING: Once the memory array is

erased, the device is programmed (to a logical “0”) on a

byte-by-byte basis. Please note that a data “0” cannot be

programmed back to a “1”; only erase operations can con-

vert “0”s to “1”s. Programming is accomplished via the

internal device command register and is a 4 bus cycle

operation (please refer to the Command Definitions table).

The device will automatically generate the required internal

program pulses.

The program cycle has addresses latched on the falling

edge of WE or CE, whichever occurs last, and the data

latched on the rising edge of WE or CE, whichever occurs

first. Programming is completed after the specified tBP cycle

time. The DATA polling feature may also be used to indi-

cate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT: The device

has one designated block that has a programming lockout

feature. This feature prevents programming of data in the

designated block once the feature has been enabled. The

size of the block is 16K bytes. This block, referred to as the

boot block, can contain secure code that is used to bring up

the system. Enabling the lockout feature will allow the boot

code to stay in the device while data in the rest of the

device is updated. This feature does not have to be acti-

vated; the boot block’s usage as a write protected region is

optional to the user. The address range of the boot block is

00000 to 03FFF for the AT49F001(N) while the address

3

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