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AD9125BCPZ View Datasheet(PDF) - Analog Devices

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AD9125BCPZ Datasheet PDF : 56 Pages
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SYNCHRONIZATION WITH DIRECT CLOCKING
When directly sourcing the DAC sample rate clock, a separate
REFCLK input signal is required for synchronization. To
synchronize devices, the DACCLK signal and the REFCLK
signal must be distributed with low skew to all of the devices
being synchronized. If the devices need to be synchronized
to a master clock, then use the master clock directly for generating
the REFCLK input (see Figure 83).
DATA RATE MODE SYNCHRONIZATION
The Procedure for Data Rate Synchronization when Directly
Sourcing the DAC Sampling Clock section outlines the steps
required to synchronize multiple devices in data rate mode. The
procedure assumes that the DACCLK and REFCLK signals are
applied to all of the devices. The procedure must be carried out
on each individual device.
Procedure for Data Rate Synchronization When Directly
Sourcing the DAC Sampling Clock
To synchronize all devices,
1. Configure the device for data rate mode and periodic
synchronization by writing 0xC0 to the Sync Control 1
register (Register 0x10). Additional synchronization
options are available and are described in the Additional
Synchronization Features section.
2. Poll the sync locked bit (Register 0x12, Bit 6) to verify that
the device is back-end synchronized. A high level on this bit
indicates that the clocks are running with a constant, known
phase relative to the sync signal.
3. Reset the FIFO by strobing the FRAME signal high for
the time required to write two complete input data-words.
Resetting the FIFO ensures that the correct data is being
read from the FIFO of each of the devices simultaneously.
AD9125
To ensure that each DAC is updated with the correct data on
the same CLK edge, two timing relationships must be met on
each DAC. DCI and D[31:0] must meet the setup and hold
times with respect to the rising edge of DACCLK, and REFCLK
must meet the setup and hold times with respect to the rising
edge of DACCLK. When resetting the FIFO, the FRAME signal
must be held high for the time required to input two complete
input data-words. When these conditions are met, the outputs
of the DACs are updated within tSKEW + tOUTDLY of each other. A
timing diagram that illustrates the timing requirements of the
input signals is shown in Figure 84.
Figure 84 shows the synchronization signal timing with 2×
interpolation; therefore, fDCI = ½ × fCLK. The REFCLK input is
shown to be equal to the data rate. The maximum frequency at
which the device can be resynchronized in data rate mode can
be expressed as
fSYNC_I = fDATA/2N
where N is any nonnegative integer.
Generally, for values of N equal to or greater than 3, select the
FIFO rate synchronization mode.
Table 26. DCI-DAC Setup and Hold Times
Minimum Setup Time, tSU_DCI
(ns)
Minimum Hold Time, tH_DCI
(ns)
0.16
0.59
DACCLKP(1)/
DACCLKN(1)
tSKEW
DACCLKP(2)/
DACCLKN(2)
REFCLKP(2)/
REFCLKN(2)
tSU_DCI
tH_DCI
DCI2(2)
tSU_SYNC tH_SYNC
FRAME(2)
Figure 84. Data Rate Synchronization Signal Timing Requirements,
2× Interpolation
Rev. 0 | Page 49 of 56
 

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