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AD9125BCPZ View Datasheet(PDF) - Analog Devices

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AD9125BCPZ Datasheet PDF : 56 Pages
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AD9125
INTERFACE TIMING
The timing diagram for the digital interface port is shown in
Figure 45. The sampling point of the data bus occurs on the
falling edge of the DCI signal and has an uncertainty of 2.1 ns,
as illustrated by the sampling interval shown in Figure 45. The
D[31:0] and FRAME signals must be valid throughout this
sampling interval.
The setup (tS) and hold (tH) times with respect to the edges
are shown in Figure 45. The minimum setup and hold times
are shown in Table 13.
DCI
D[31:0]
tS tH
FRAME
Figure 45. Timing Diagram for Input Data Ports
Table 13. Data Port Setup and Hold Times
Minimum Setup Time, tS (ns) Minimum Hold Time, tH (ns)
0.86
1.24
DCI
tS-FRAME
tH-FRAME
FRAME
Figure 46. Timing Diagram for Frame input
Table 14. FRAME Setup and Hold Times
Minimum Setup Time, tS-FRAME
(ns)
Minimum Hold Time, tH_FRAME
(ns)
−0.04
+1.05
The data interface timing can be verified by using the sample
error detection (SED) circuitry. See the Interface Timing
Validation section for details.
FIFO OPERATION
The AD9125 contains a 2-channel, 16-bit wide, eight-word-deep
FIFO designed to relax the timing relationship between the data
arriving at the DAC input ports and the internal DAC data rate
clock. The FIFO acts as a buffer that absorbs timing variations
between the data source and DAC, such as the clock-to-data
variation of an FPGA or ASIC, which significantly increases the
timing budget of the interface.
Figure 47 shows the block diagram of the datapath through the
FIFO. The data is latched into the device and is formatted, and
then it is written into the FIFO register determined by the FIFO
write pointer. The value of the write pointer is incremented every
time a new word is loaded into the FIFO. Meanwhile, data is
read from the FIFO register determined by the read pointer and
fed into the digital datapath. The value of the read pointer is
updated every time data is read into the datapath from the FIFO.
This happens at the data rate, that is, the DACCLK rate divided by
the interpolation ratio.
Valid data is transmitted through the FIFO as long as the
FIFO does not overflow or become empty. Note that an over-
flow or empty condition of the FIFO is the same as the write
pointer and read pointer being equal. When both pointers are
equal, an attempt is made to read and write a single FIFO register
simultaneously. This simultaneous register access leads to
unreliable data transfer through the FIFO and must be avoided.
Nominally, data is written to the FIFO at the same rate that data is
read from the FIFO, which keeps the data level in the FIFO constant.
If data is written to the FIFO faster than data is read, the data level
in the FIFO increases. If data is written to the device slower than
data is read, the data level in the FIFO decreases. For an optimum
timing margin, the FIFO level should be maintained near half
full, which is the same as maintaining a difference of four between
the write pointer and read pointer values.
DATA
DCI
INPUT
LATCH
32 BITS
DATA
ASSEMBLER
REG 0
REG 1
REG 2
REG 3
REG 4
REG 5
REG 6
REG 7
16
DATA 16
PATHS
DACS
WRITE POINTER
32 BITS
READ POINTER
÷ INT
DACCLK
Figure 47. Block Diagram of Datapath Through FIFO
Rev. 0 | Page 30 of 56
 

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