AD9125BCPZ View Datasheet(PDF) - Analog Devices

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AD9125BCPZ

Dual, 16-Bit, 1000 MSPS, TxDAC+ Digital-to-Analog Converter

Analog Devices 

CMOS INPUT DATA PORTS

The AD9125 input data port consists of a data clock (DCI),

data bus, and FRAME signal. The data port can be configured

to operate in three modes: dual-word mode, word mode, and

byte mode.

In dual-word mode, I and Q data is received simultaneously on

two 16-pin buses. One bus receives I datapath input words, and

the other bus receives Q datapath input words. In word mode,

one 16-pin bus is used to receive interleaved I and Q input

words. In byte mode, an 8-pin bus is used to receive interleaved

I and Q input bytes. The pin assignments of the bus in each

mode is described in Table 12.

Table 12. Data Bit Pin Assignments for Data Input Modes

Mode

Data Bus Pin Assignments

Dual Word I data: D[31:16]

Q data: D[15:0]

Word

I and Q data: D[29:28], D[25:24], D[21:20], D[17:16],

D[15:14], D[11:10], D[7:6], D[3:2]

Byte

I and Q data: D[21:20], D[17:16], D[15:14], D[11:10]

In byte and word modes, a FRAME signal is required for

controlling which DAC receives the data. In dual-word mode,

the FRAME signal is not required because each DAC has a

dedicated bus.

DUAL-WORD MODE

In dual-word mode, the DCI signal is supplied as a qualifying

clock that is time aligned with the input data. The rising edge of

the DCI signal should be aligned with the changing data of each

of the I and Q input data streams.

DCI

I DATA

I1

I2

I3

Q DATA

Q1

Q2

Q3

Figure 42. Timing Diagram for Dual-Word Mode

AD9125

WORD MODE

In word mode, the DCI signal is supplied as a qualifying clock

that is time aligned with the input data. The rising edge of the

DCI signal should be aligned with the changing data of the

interleaved I and Q input data stream. The FRAME signal

indicates to which DAC the data is sent. When FRAME is high,

data is sent to the I DAC. When FRAME is low, data is sent to

the Q DAC. For 14- and 12-bit resolution devices, the two and

four LSBs are not significant, respectively. The complete timing

diagram is shown in Figure 43.

DCI

I AND

Q DATA

I1

Q1

I2

FRAME

Figure 43. Timing Diagram for Word Mode

BYTE MODE

In byte mode, the DCI signal is supplied as a qualifying clock

that is time aligned with the input data. The rising edge of the

DCI signal should be aligned with the changing data of the

interleaved I and Q input data stream. The FRAME signal

indicates to which DAC the data is sent. When FRAME is high,

data is sent to the I DAC. When FRAME is low, data is sent to

the Q DAC. Both bytes must be written to each datapath for

proper operation. For 14- and 12-bit resolution devices, the

LSBs in the second byte are not significant. The complete

timing diagram is shown in Figure 44.

DCI

Q

I AND

DATA

QLSB

I1MSB

I1LSB Q1MSB Q1LSB

I2MSB

I2LSB Q2MSB Q2LSB

FRAME

Figure 44. Timing Diagram for Byte Mode

Rev. 0 | Page 29 of 56

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