AD9106
Data Sheet
FSADJ4 Register (DAC4RSET, Address 0x09)
Table 24. Bit Descriptions for DAC4RSET
Bits Bit Field Name Settings Description
15
DAC4_RSET_EN
For write, enable the internal RSET resistor for DAC4; for read, RSET for
DAC4 is enabled during calibration mode.
[14:13] RESERVED
[12:8] DAC4_RSET_CAL
[7:5] RESERVED
Digital control value of RSET resistor for DAC4 after calibration—read only.
[4:0] DAC4_RSET
Digital control to set the value of RSET resistor in DAC4.
Reset
0x00
0x00
0x00
0x00
0x0A
Access
RWE
A
RWE
A
R
RWE
A
RWE
A
FSADJ3 Register (DAC3RSET, Address 0x0A)
Table 25. Bit Descriptions for DAC3RSET
Bits Bit Field Name Settings Description
15
DAC3_RSET_EN
For write, enable the internal RSET resistor for DAC3; for read, RSET for
DAC3 is enabled during calibration mode.
[14:13] RESERVED
[12:8] DAC3_RSET_CAL
Digital control value of RSET resistor for DAC3 after calibration—read only.
[7:5] RESERVED
[4:0] DAC3_RSET
Digital control to set the value of RSET resistor in DAC3.
Reset
0
0x0
0x00
0x0
0x0A
Access
RWE
A
RWE
A
R
RWE
A
RWE
A
FSADJ2 Register (DAC2RSET, Address 0x0B)
Table 26. Bit Descriptions for DAC2RSET
Bits Bit Field Name Settings Description
15
DAC2_RSET_EN
For write, enable the internal RSET resistor for DAC2; for read, RSET for
DAC2 is enabled during calibration mode.
[14:13] RESERVED
[12:8] DAC2_RSET_CAL
Digital control value of RSET resistor for DAC2 after calibration—read only.
[7:5] RESERVED
[4:0] DAC2_RSET
Digital control to set the value of RSET resistor in DAC2.
Reset
0
0x0
0x00
0x0
0xA
Access
RWE
A
RWE
A
R
RWE
A
RWE
A
FSADJ1 Register (DAC1RSET, Address 0x0C)
Table 27. Bit Descriptions for DAC1RSET
Bits Bit Field Name Settings Description
15
DAC1_RSET_EN
For write, enable the internal RSET resistor for DAC1; for read, RSET for DAC1
is enabled during calibration mode.
[14:13] RESERVED
[12:8] DAC1_RSET_CAL
Digital control value of RSET resistor for DAC1 after calibration—read only.
[7:5] RESERVED
[4:0] DAC1_RSET
Digital control to set the value of RSET resistor in DAC1.
Reset
0x00
0x00
0x00
0x0
0x0A
Access
RWE
A
RWE
A
R
RWE
A
RWE
A
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