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908E625 View Datasheet(PDF) - Freescale Semiconductor

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908E625 Datasheet PDF : 48 Pages
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ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
908E625
Introduction
This thermal addendum ia provided as a supplement to the MM908E625
technical data sheet. The addendum provides thermal performance information
that may be critical in the design and development of system applications. All
electrical, application and packaging information is provided in the data sheet.
54-PIN
SOICW-EP
Package and Thermal Considerations
This MM908E625 is a dual die package. There are two heat sources in the
package independently heating with P1 and P2. This results in two junction
temperatures, TJ1 and TJ2, and a thermal resistance matrix with RθJAmn.
For m, n = 1, RθJA11 is the thermal resistance from Junction 1 to the reference
temperature while only heat source 1 is heating with P1.
For m = 1, n = 2, RθJA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P2. This applies to
RθJ21 and RθJ22, respectively.
DWB SUFFIX
EK SUFFIX (Pb-Free)
98ARL105910
54-PIN SOICW-EP
TJ1
TJ2
=
RθJA11 RθJA12 . P1
RθJA21 RθJA22
P2
Note For package dimensions, refer to the
908E625 device datasheet.
The stated values are solely for a thermal performance comparison of one
package to another in a standardized environment. This methodology is not
meant to and will not predict the performance of a package in an application-specific environment. Stated values were obtained
by measurement and simulation according to the standards listed below.
Standards
Table 14. Thermal Performance Comparison
Thermal
Resistance
1 = Power Chip, 2 = Logic Chip [°C/W]
m = 1,
n=1
m = 1, n = 2
m = 2, n = 1
m = 2,
n=2
RθJAmn (1)(2)
23
20
24
RθJBmn (2)(3)
9.0
6.0
10
RθJAmn (1)(4)
52
47
52
RθJCmn (5)
1.0
0
2.0
Notes:
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5. Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
1.0
1.0
0.2
0.2
* All measurements
are in millimeters
Soldermast
openings
Thermal vias
connected to top
54 Terminal SOIC-EP
buried plane
0.65 mm Pitch
17.9 mm x 7.5 mm Body
10.3 mm x 5.1 mm Exposed Pad
Figure 27. Thermal Land Pattern for Direct Thermal
Attachment Per JEDEC JESD51-5Thermal Test Board
908E625
46
Analog Integrated Circuit Device Data
Freescale Semiconductor
 

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