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74LVT373SJX View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
View to exact match
74LVT373SJX Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
September 1999
Revised November 2000
74LVT373 74LVTH373
Low Voltage Octal Transparent Latch
with 3-STATE Outputs
General Description
The LVT373 and LVTH373 consist of eight latches with
3-STATE outputs for bus organized system applications.
The latches appear transparent to the data when Latch
Enable (LE) is HIGH. When LE is LOW, the data satisfying
the input timing requirements is latched. Data appears on
the bus when the Output Enable (OE) is LOW. When OE is
HIGH, the bus output is in a high impedance state.
The LVTH373 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
These octal latches are designed for low-voltage (3.3V)
VCC applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT373 and LVTH373
are fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH373),
also available without bushold feature (74LVT373).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink 32 mA/+64 mA
s Functionally compatible with the 74 series 373
s ESD performance:
Human-body model > 2000V
Machine model > 200V
Charged-device model > 1000V
Ordering Code:
Order Number
74LVT373WM
74LVT373SJ
74LVT373MTC
74LVTH373WM
74LVTH373SJ
74LVTH373MTC
Package Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Logic Symbols
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation DS012015
www.fairchildsemi.com
 

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