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CAT24WC01 View Datasheet(PDF) - Catalyst Semiconductor => Onsemi

Part Name
Description
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CAT24WC01
Catalyst
Catalyst Semiconductor => Onsemi Catalyst
CAT24WC01 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
CAT24WC01/02/04/08/16
FUNCTIONAL DESCRIPTION
The CAT24WC01/02/04/08/16 supports the I2C Bus
data transmission protocol. This Inter-Integrated Circuit
Bus protocol defines any device that sends data to the
bus to be a transmitter and any device receiving data to
be a receiver. Data transfer is controlled by the Master
device which generates the serial clock and all START
and STOP conditions for bus access. The CAT24WC01/
02/04/08/16 operates as a Slave device. Both the Mas-
ter and Slave devices can operate as either transmitter
or receiver, but the Master device controls which mode
is activated. A maximum of 8 devices (CAT24WC01 and
CAT24WC02), 4 devices (CAT24WC04), 2 devices
(CAT24WC08) and 1 device (CAT24WC16) may be
connected to the bus as determined by the device
address inputs A0, A1, and A2.
PIN DESCRIPTIONS
SCL: Serial Clock
The CAT24WC01/02/04/08/16 serial clock input pin is
used to clock all data transfers into or out of the device.
This is an input pin.
SDA: Serial Data/Address
The CAT24WC01/02/04/08/16 bidirectional serial data/
address pin is used to transfer data into and out of the
device. The SDA pin is an open drain output and can be
wire-ORed with other open drain or open collector
outputs.
A0, A1, A2: Device Address Inputs
These inputs set device address when cascading mul-
tiple devices. When these pins are left floating the
default values are zeros.
A maximum of eight devices can be cascaded when
Figure 1. Bus Timing tF
SCL
tSU:STA
SDA IN
SDA OUT
tHIGH
tR
tLOW
tLOW
tHD:DAT
tHD:STA
tSU:DAT
tAA
tDH
Figure 2. Write Cycle Timing
tSU:STO
tBUF
5020 FHD F03
SCL
SDA
8TH BIT
BYTE n
ACK
Figure 3. Start/Stop Timing
Doc. No. 1022, Rev. J
SDA
SCL
START BIT
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
5020 FHD F04
STOP BIT
5020 FHD F05
4
 

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