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MT7620 View Datasheet(PDF) - MediaTek Inc

Part NameDescriptionManufacturer
MT7620 Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip MediaTek
MediaTek Inc MediaTek
MT7620 Datasheet PDF : 54 Pages
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MT7620 DATASHEET
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.5.9.1 Pin share function description
Pin Share Name
I/O Pin Share Function description
PCMDTX
O PCM Data Transmit
DATA signal sent from the PCM host to the external codec.
PCMDRX
I PCM Data Receive
DATA signal sent from the external codec to the PCM host.
PCMCLK
I/O PCM Clock
The clock signal can be generated by the PCM host (Output direction), or
provided by an external clock (input direction). The clock frequency should match
the slot configuration of the PCM host.
e.g.
4 slots, PCM clock out/in should be 256 kHz.
8 slots, PCM clock out/in should be 512 kHz.
16 slots, PCM clock out/in should be 1.024 MHz.
32 slots, PCM clock out/in should be 2.048 MHz.
64 slots, PCM clock out/in should be 4.096 MHz.
128 slots, PCM clock out/in should be 8.192 MHz.
PCMFS
I2SSDI
I2SSDO
I2SWS
I2SCLK
I/O PCM SYNC signal.
In our design, the direction of this signal is independent of the direction of
PCMCLK. Its direction and mode is configurable.
I
I2S Data input
O I2S Data output
I/O I2S Channel Selection (or Word selection)
In master mode the pin data direction is set to output, in slave mode it is set to
input.
I/O I2S clock
In master mode the pin data direction is set to output, in slave mode it is set to
input.
WDT_RST_N
I/O Watchdog timeout reset
ND_D7
I/O Nand flash control data bit7
ND_D6
I/O Nand flash control data bit6
ND_D5
I/O Nand flash control data bit5
ND_D4
I/O Nand flash control data bit4
ND_ALE
I/O Nand flash Address Latch Enable
ND_CLE
I/O Nand flash Command Latch Enable
DSMT7620_V.1.3_091212
loginid=yj.huo@z-linkelec.com,time=2012-11-23 11:46:26,ip=14.153.195.177,doctitle=MT7620_Datasheet_20121114.pdf,company=Z-Link Limited 香港瑞聯電子_RLT
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