MT7620 View Datasheet(PDF) - MediaTek Inc
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MT7620 Datasheet PDF : 54 Pages
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MT7620 DATASHEET
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
2.5.3 RGMII pin share schemes
Controlled by the RGMII1_GPIO_MODE register.
Pin Name
1’b0 RGMII1 1’b1 GPIO
GE1_RXCLK
GE1_RXCLK
GPIO#35
GE1_RXDV
GE1_RXDV
GPIO#34
GE1_RXD 0 to 3 GE1_RXD 0 to 3 GPIO#33 to 30
GE1_TXCLK
GE1_TXCLK
GPIO#29
GE1_TXDV
GE1_TXDV
GPIO#28
GE1_TXD0 to 3 GE1_TXD0 to 3 GPIO#27 to 24
NOTE: This scheme applies only to the TFBGA package.
Controlled by the RGMII2_GPIO_MODE register.
Pin Name
1’b0 RGMII2 1’b1 GPIO
GE2_RXCLK
GE2_RXCLK
GPIO#71
GE2_RXDV
GE2_RXDV
GPIO#70
GE2_RXD0 to 3 GE2_RXD0 to 3 GPIO#69 to 66
GE2_TXCLK
GE2_TXCLK
GPIO#65
GE2_TXDV
GE2_TXDV
GPIO#64
GE2_TXD0 to 3 GE2_TXD0 to 3 GPIO#63 to 60
NOTE: This scheme applies only to the TFBGA package.
2.5.4 WDT_RST_MODE pin share scheme
Controlled by the WDT_RST _MODE register.
Pin Name
2’b00
WDT_RST_N
WDT_RST_N
2.5.5 PERST_N pin share scheme
Controlled by the PERST_GPIO_MODE register.
Pin Name
2’b00
PERST_N
PERST_N
NOTE: This scheme applies only to the TFBGA package.
2.5.6 MDC/MDIO pin share scheme:
Controlled by the the MDIO_GPIO_MODE register.
Pin Name
2’b00
MDC
MDC
MDIO
MDIO
2’b01
REFCLK0_OUT
2’b01
REFCLK0_OUT
2’b01
REFCLK0_OUT
REFCLK1_OUT
2’b1x
GPIO#17
2’b1x
GPIO#36
2’b1x
GPIO #23
GPIO #24
DSMT7620_V.1.3_091212
loginid=yj.huo@z-linkelec.com,time=2012-11-23 11:46:26,ip=14.153.195.177,doctitle=MT7620_Datasheet_20121114.pdf,company=Z-Link Limited 香港瑞聯電子_RLT
Page 25 of 54
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