12.2
Embedded Characteristics
Tight integration of system peripherals reduces area and development costs
Thumb instruction set combines high code density with 32-bit performance
IEEE754-compliant single-precision FPU
Code-patch ability for ROM system updates
Power control optimization of system components
Integrated sleep modes for low power consumption
Fast code execution permits slower processor clock or increases sleep mode time
Hardware division and fast digital-signal-processing oriented multiply accumulate
Saturating arithmetic for signal processing
Deterministic, high-performance interrupt handling for time-critical applications
Memory Protection Unit (MPU) for safety-critical applications
Extensive debug and trace capabilities:
Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging, tracing, and
code profiling.
12.3 Block Diagram
Figure 12-1. Typical Cortex-M4F Implementation
Cortex-M4F
Processor
FPU
NVIC
Processor
Core
Debug
Access
Port
Memory
Protection Unit
Serial
Wire
Viewer
Flash
Patch
Data
Watchpoints
Code
Interface
Bus Matrix
SRAM and
Peripheral Interface
SAM4CP [DATASHEET] 50
43051E–ATPL–08/14