SAM4CP16B View Datasheet(PDF) - Atmel Corporation

Part Name

Description

View to exact match

SAM4CP16B

SMART Power Line Communications Device

Atmel Corporation 

8.1.5.5 Typical Execution View

Figure 8-5 below provides the code execution view for both Cortex-M4 cores. AHB to APB, AHB to AHB and Matrices are

not represented in this view.

Figure 8-5. Execution View

SRAM0

Core 0,

RW Data,

Stack, Heap

S-Bus

ICode / DCode Bus

Core 0

Application

Core

(Cortex-M4)

MPU NVIC

S-Bus

Cache

Ctrl.

(CMCC0)

Flash

Core 0

Code,

RO Data

Core 1

Code,

RO Data

Core 1

Application

Binary

SRAM2

Core 1,

RW Data,

Stack, Heap

Core 0 <--> Core 1

Msg. Buffer (1)

Cache

Ctrl.

(CMCC1)

ICode / DCode Bus

ICode / DCode Bus

Core 1

Coprocessor

Core

(Cortex-M4F)

FPU NVIC

S-Bus

SRAM1

Core 1

Code,

RO Data

Sub-system 0

Sub-system 1

Note: 1. SRAM0 can also be used as Message Buffer Exchange.

Note: Matrices, AHB and APB Bridges are not represented.

SAM4CP [DATASHEET] 38

43051E–ATPL–08/14

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