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SAM4CP16B View Datasheet(PDF) - Atmel Corporation

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SAM4CP16B
Atmel
Atmel Corporation Atmel
SAM4CP16B Datasheet PDF : 1069 Pages
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6.2.1
Serial Wire JTAG Debug Port (SWJ-DP) and Serial Wire Debug Port (SW-DP) Pins
The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/TRACESWO, TDI and commonly provided on a standard 20-pin
JTAG connector defined by ARM. For more details about voltage reference and reset state, refer to Table 11-6,
“Multiplexing on PIO Controller B (PIOB)”.
At start-up, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging probe. Refer to the
“Debug and Test” section of this datasheet.
SWJ-DP pins can be used as standard I/Os to provide users with more general input/output pins when the debug port is
not needed in the end application. Mode selection between SWJ-DP mode (System IO mode) and general IO mode is
performed through the AHB Matrix Special Function Registers (MATRIX_SFR). Configuration of the pad for pull-up,
triggers, debouncing and glitch filters is possible regardless of the mode.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent
pull-down resistor of about 15 kto GND, so that it can be left unconnected for normal operations.
By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial Wire Debug Port, it must
provide a dedicated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables the JTAG-DP and enables the
SW-DP. When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace.
The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace can only be used
with SW-DP, not JTAG-DP. For more information about SW-DP and JTAG-DP switching, refer to the “Debug and Test”
section of this datasheet. The SW-DP/SWJ-DP pins are used for debug access to both cores.
6.3 Test Pin
The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the SAM4CP
series. For details on entering fast programming mode, see the “Fast Flash Programming Interface (FFPI)” section of this
datasheet. For more information on the manufacturing and test modes, refer to the “Debug and Test” section of this
datasheet.
6.4 NRST Pin
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal
to the external components or asserted low externally to reset the microcontroller. It resets the core and the peripherals
except the Backup region (RTC, RTT and Supply Controller). There is no constraint on the length of the reset pulse and
the Reset controller can guarantee a minimum pulse length. The NRST pin integrates a permanent pull-up resistor to
VDDIO of about 100 k. By default, the NRST pin is configured as an input.
6.5 TMPx Pins: Anti-tamper Pins
Anti-tamper pins detect intrusion, for example, into a smart meter case. Upon detection through a tamper switch,
automatic, asynchronous and immediate clear of registers in the backup area, and time stamping in the RTC will be
performed. Anti-tamper pins can be used in all modes. Date and number of tampering events are stored automatically.
Anti-tampering events can be programmed so that half of the General Purpose Backup Registers (GPBR) are erased
automatically. TMP1 to TMP3 signals are shared with a PIO pin meaning that VDDIO must be supplied, whereas TMP0
is in the VDDBU domain.
6.6 RTCOUT0 Pin
The RTCOUT0 pin shared in the PIO (supplied by VDDIO) can be used to generate waveforms from the RTC in order to
take advantage of the RTC inherent prescalers while the RTC is the only powered circuitry (low-power mode of
operation, backup mode) or in any active mode. Entering backup or low-power operating modes does not affect the
waveform generation outputs (VDDIO needs still to be supplied). Anti-tampering pin detection can be synchronised with
this signal.
Note: To use the RTCOUT0 signal during application development via JTAG-ICE interface, the programmer must use
Serial Wire Debug (SWD) mode. In this case, the TDO pin is not used as a JTAG signal by the ICE interface.
SAM4CP [DATASHEET] 27
43051E–ATPL–08/14
 

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