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TPS3307-18-EP View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
TPS3307-18-EP TRIPLE PROCESSOR SUPERVISORS TI
Texas Instruments TI
TPS3307-18-EP Datasheet PDF : 18 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
TPS3307Ć18ĆEP, TPS3307Ć33ĆEP
TRIPLE PROCESSOR SUPERVISORS
SGLS140A − NOVEMBER 2002 − REVISED AUGUST 2005
timing requirements at VDD = 2 V to 6 V, RL = 1 M, CL = 50 pF, TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
SENSEn
tw
Pulse width
MR
VSENSEnL = VIT− −0.2 V,
VIH = 0.7 × VDD,
VSENSEnH = VIT+ + 0.2 V
VIL = 0.3 × VDD
6
100
TYP MAX UNIT
µs
ns
switching characteristics at VDD = 2 V to 6 V, RL = 1 M, CL = 50 pF, TA = 25°C
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
td
tPHL
tPLH
Delay time
Propagation (delay) time,
high-to-low level output
Propagation (delay) time,
low-to-high level output
MR to RESET
MR to RESET
VI(SENSEn) VIT+ + 0.2 V,
MR 0.7 × VDD, See timing diagram
140 200 280 ms
VI(SENSEn) VIT+ + 0.2 V,
VIH = 0.7 × VDD, VIL = 0.3 × VDD
200 600 ns
tPHL
tPLH
Propagation (delay) time,
high-to-low level output
Propagation (delay) time,
low-to-high level output
SENSEn to RESET
SENSEn to RESET
VIH VIT+ + 0.2 V, VIL VIT− − 0.2 V,
MR 0.7 × VDD
1
5 µs
6
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