TDA5251F1 View Datasheet(PDF) - Infineon Technologies

Part Name

Description

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TDA5251F1

ASK/FSK 315MHz Wireless Transceiver

Infineon Technologies 

TDA5251 F1

Version 1.1

Functional Description

Table 2-29 CLK_DIV Output Selection

D5

D4

Output

0

0

Output from Divider (default)

0

1

13.125MHz

1

0

32kHz

1

1

Window Count Complete

Note: Data are valid 500 µs after the crystal oscillator is enabled (see Figure 2-15 and Figure 2-

16, tCLKSU).

Table 2-30 CLK_DIV Setting

D3 D2 D1 D0 Total Divider Ratio

0

0

0

0

2

0

0

0

1

4

0

0

1

0

6

0

0

1

1

8

0

1

0

0

10

0

1

0

1

12

0

1

1

0

14

0

1

1

1

16

1

0

0

0

18

1

0

0

1

20

1

0

1

0

22

1

0

1

1

24

1

1

0

0

26

1

1

0

1

28

1

1

1

0

30

1

1

1

1

32

Output Frequency [MHz]

6.6

3.3

2.2

1.6

1.3

1.1

0.94

0.82

0.730 (default)

0.66

0.6

0.,55

0.5

0.47

0.44

0.41

Note: As long as default settings are used, there is no clock available at the clock output during

Power Down. It is possible to enable the clock during Power Down by setting CLK_EN (Bit D9) in

the Config Register (00H) to HIGH.

2.4.20 RSSI and Supply Voltage Measurement

The input of the 6Bit-ADC can be switched between two different sources: the RSSI voltage (default

setting) or a resistor network dividing the Vcc voltage by 5.

Table 2-31 Source for 6Bit-ADC Selection (Register 08H)

SELECT

Input for 6Bit-ADC

0

Vcc / 5

1

RSSI (default)

Data Sheet

35

2007-02-26

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