TDA5251F1 View Datasheet(PDF) - Infineon Technologies
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TDA5251F1 Datasheet PDF : 88 Pages
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TDA5251 F1
Version 1.1
Functional Description
This means that the device needs tDDSU setup time to start the data detection after RX is activated.
When activating TX it requires tTXSU setup time to enable the power amplifier.
For timing information refer to Table 4-3.
For test purposes a TESTMODE is provided by the Sequencer as well. In this mode the BLOCK_PD
register be set to various values. This will override the Sequencer timing. Depending on the settings
in Config Register 00H the corresponding building blocks are enabled, as shown in the subsequent
figure.
RESET
32 kHz
RX ON
TX ON
ASK/FSK
RC- OSC.
2
XTAL FREQU.
16
SELECT
16
INTERNAL BUS
16
Figure 2-17 Sequencer‘s capability
2.4.19 Clock Divider
It supports an external logic with a programmable Clock at pin 26 (CLKDIV).
INTERNAL BUS
13 MHz
4 BIT
COUNTER
32 kHz
WINDOW COUNT COMPLETE
CLKDiv
26
Figure 2-18 Clock Divider
The Output Selection and Divider Ratio can be set in the CLK_DIV register.
sequencer_raw.wmf
clk_div.wmf
Data Sheet
34
2007-02-26
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