TDA5251F1 View Datasheet(PDF) - Infineon Technologies

Part Name

Description

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TDA5251F1

ASK/FSK 315MHz Wireless Transceiver

Infineon Technologies 

TDA5251 F1

Version 1.1

Functional Description

Note: The time delay between start of ON time and the 15µs LOW impulse is 2.6ms + 3 period of

data rate.

If ADC & Data Detect Logic are in continuous mode the 15µs LOW impulse is applied at PwdDD

after each data valid decision.

In self polling mode if D9=0 (Register 00h) and when PwdDD pin level is HIGH the CLK output is

on during ON time and off during OFF time. If D9=1, the CLK output is always on.

TIMER MODE: Only the internal Timer (determined by the ON_TIME and OFF_TIME registers) is

active to support an external logic with periodical Interrupts. After ON_TIME + OFF_TIME a 15µs

LOW impulse is applied at the PwdDD pin (Pin 27).

Action

PwdDD pin in

TIMER MODE

ON_TIME

OFF_TIME

ON_TIME

Register 04H

Register 05H

Register 04H

t

15µs

t

15µs

Figure 2-11 Timing for Timer Mode

timing_timermode.wmf

2.4.17 Data Valid Detection, Data Pin

Data signals generate a typical spectrum and this can be used to determine if valid data is on air.

Amplitude

RSSI

Frequency & RSSI Window

DATA on air

no DATA on air

Frequency

f

data_rate_detect.wmf

Figure 2-12 Frequency and RSSI Window

The “data valid” criterion is generated from the result of RSSI-TH3 comparison and tGATE between

TH1 and TH2 result as shown below. In case of Manchester coding the 0,5*TH1 and 0,5*TH2 gives

improved performance.

The use of permanent data valid recognition makes it absolutely necessary to set the RSSI-ADC

and the Window counter into continuous mode (Register 00H, Bit D5 = D6 = 1).

Data Sheet

31

2007-02-26

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