STA339BW
Register description
Note:
7.2.4
To avoid any audio side effects (like pop noise), it is strongly recommended to soft mute any
audio streams flowing into STA339BW data path before the desynchronization event
happens. At the same time any processing related to the I2C configuration should be issued
only after the serial audio interface and the internal PLL are synchronous again.
Any mute or volume change causes some delay in the completion of the I2C operation due
to the soft volume feature. The soft volume phase change must be finished before any clock
desynchronization.
Delay serial clock enable
Bit R/W
5
R/W
Table 22. Delay serial clock enable
RST
Name
Description
0
DSCKE
0: No serial clock delay
1: Serial clock delay by 1 core clock cycle to tolerate
anomalies in some I2S master devices
7.2.5
Channel input mapping
Bit R/W
6
R/W
7
R/W
Table 23. Channel input mapping
RST
Name
Description
0
C1IM
1
C2IM
0: Processing channel 1 receives Left I2S Input
1: Processing channel 1 receives Right I2S Input
0: Processing channel 2 receives Left I2S Input
1: Processing channel 2 receives Right I2S Input
Each channel received via I2S can be mapped to any internal processing channel via the
Channel Input Mapping registers. This allows for flexibility in processing. The default
settings of these registers map each I2S input channel to its corresponding processing
channel.
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