STA339BWTR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
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STA339BWTR
STMicroelectronics
STA339BWTR Datasheet PDF : 78 Pages
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Register description
STA339BW
7.1
Configuration register A (addr 0x00)
7.1.1
D7
D6
D5
D4
FDRB
TWAB
TWRB
IR1
0
1
1
0
D3
D2
D1
D0
IR0
MCS2
MCS1
MCS0
0
0
1
1
Master clock select
Bit
0
1
2
R/W
R/W
R/W
R/W
RST
1
1
0
Table 11. Master clock select
Name
Description
MCS0
MCS1
MCS2
Selects the ratio between the input I2S sample
frequency and the input clock.
The STA339BW supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,
176.4 kHz, and 192 kHz. Therefore the internal clock is:
32.768 MHz for 32 kHz
45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz
49.152 MHz for 48 kHz, 96 kHz, and 192 kHz
The external clock frequency provided to the XTI pin must be a multiple of the input sample
frequency (fs).
The relationship between the input clock and the input sample rate is determined by both
the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor
generating the internal clock and the IR bit determines the oversampling ratio used
internally.
Input sample rate
fs (kHz)
-
32, 44.1, 48
88.2, 96
176.4, 192
Table 12. Input sampling rates
IR
MCS[2:0]
-
101
100
011
010
001
000
00 576 * fs 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs
01 NA
64 * fs 128 * fs 192 * fs 256 * fs 384 * fs
1X NA
32 * fs 64 * fs 96 * fs 128 * fs 192 * fs
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