# MAX1470 查看數據表（PDF） - Maxim Integrated

MAX1470 Datasheet PDF : 12 Pages
315MHz Low-Power, +3V Superheterodyne
Cspec, the frequency pulling equals zero.
Data Filter
The data filter is implemented as a 2nd-order lowpass
Sallen-Key filter. The pole locations are set by the combi-
nation of two on-chip resistors and two external capaci-
tors. Adjusting the value of the external capacitors
changes the corner frequency to optimize for different
data rates. The corner frequency should be set to
approximately 1.5 times the fastest expected data rate
from the transmitter. Keeping the corner frequency near
the data rate rejects any noise at higher frequencies,
resulting in an increase in receiver sensitivity.
The configuration shown in Figure 1 can create a
Butterworth or Bessel response. The Butterworth filter
offers a very flat amplitude response in the passband
and a roll-off rate of 40dB/decade for the two-pole filter.
The Bessel filter has a linear phase response, which
works well for filtering digital data. To calculate the
value of C5 and C6, use the following equations along
with the coefficients in Table 1:
( )( )( ) C5 =
b
a 100kΩ π fc
( )( )( ) C6 =
a
4 100kΩ π fc
where fC is the desired 3dB corner frequency.
For example, to choose a Butterworth filter response
with a corner frequency of 5kHz:
( )( )( )( ) C5 =
1.000
450pF
1.414 100k3.14 5kHz
( )( )( )( ) C6 =
1.414
225pF
4 100k3.14 5kHz
Table 1. Coefficents to Calculate C5 and C6
FILTER TYPE
Butterworth
(Q = 0.707)
Bessel
(Q = 0.577)
a
1.414
1.3617
b
1.000
0.618
RDF2 100kRDF1 100k
19
21
22
DSP
OPP
DF
C6
C5
Figure 1. Sallen-Key Lowpass Data Filter
Choosing standard capacitor values changes C5 to
470pF and C6 to 220pF, as shown in the Typical
Application Circuit.
Data Slicer
The purpose of the data slicer is to take the analog out-
put of the data filter and convert it to a digital signal.
This is achieved by using a comparator and comparing
voltage is set by the voltage on DSN, which is connect-
ed to the negative input of the data slicer comparator.
The positive input is connected to the output of the data
filter internally, and also the DSP pin for use with some
data slicer configurations.
The suggested data slicer configuration uses a resistor
(R1) connected between DSN and DSP with a capaci-
tor (C4) from DSN to DGND (Figure 2). This configura-
tion averages the analog output of the filter and sets the
threshold to approximately 50% of that amplitude. With
this configuration, the threshold automatically adjusts
as the analog signal varies, minimizing the possibility
for errors in the digital data. The sizes of R1 and C4
affect how fast the threshold tracks the analog ampli-
tude. Be sure to keep the corner frequency of the RC
circuit lower than the lowest expected data rate.
Note that a long string of zeros or ones can cause the
threshold to drift. This configuration works best if a cod-
ing scheme, such as Manchester code, which has an
equal number of zeros and ones, is used.
Peak Detector
The peak detector output (PDOUT), in conjunction with
an external RC filter, creates a DC output voltage equal
to the peak value of the data signal. The resistor pro-
vides a path for the capacitor to discharge, allowing the
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