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IDT5V9888 View Datasheet(PDF) - Integrated Device Technology

Part NameIDT5V9888 IDT
Integrated Device Technology IDT
IDT5V9888 Datasheet PDF : 37 Pages
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Pre-Divider (D) Values
1 - 255
1 - 255
1 - 255
Multiplier (M) Values
2 - 8190
2 - 8190
1 - 4095
Programmable Loop Bandwidth
Spread Spectrum
Generation Capability
The 5V9888 supports up to two clock inputs. One of the clock inputs (XTALIN/
REFIN) can be driven by either an external crystal or a reference clock. The
second clock input (CLKIN) can only be driven from an external reference clock.
Either clock input can be set as a the primary clock. The primary clock
designation is to establish which is the main reference clock to the PLLs. The
non-primary clock is designated as the secondary clock in case the primary clock
goes absent and a backup is needed. The PRIMCLK bit (0x34) determines
which clock input will be the primary clock. When PRIMCLK bit is "0", it will select
XTALIN/REFIN as the primary, and when "1", it will select CLKIN as the primary.
The two external reference clocks can be manually selected using the GIN4/
CLK_SEL pin, except in Manual Frequency Control (MFC) mode 2, or via
programming by hard wiring the CLK_SEL pin and toggling the PRIMCLK bit.
For more details on the MFC modes, refer to the CONFIGURING MULTI-
PURPOSE I/Os section. When CLK_SEL is LOW, the primary clock is selected
and when HIGH, the secondary clock is selected. The SM bits (0x34) must be
set to "0x" for manual switchover which is detailed in SWITCHOVER MODES
Selected Clock Input
Crystal Input (XTALIN/REFIN)
The crystal oscillators should be fundamental mode quartz crystals: overtone
crystals are not suitable. Crystal frequency should be specified for parallel
resonance with 50Ω maximum equivalent series resonance.
When the XTALIN/REFIN pin is driven by a crystal, it is important to set the
internal oscillator inverter drive strength and internal tuning/load capacitor
values correctly to achieve the best clock performance. These values are
programmable through either I2C or JTAG interface to allow for maximum
compatibility with crystals from various manufacturers, processes, performances,
and qualities. The internal load capacitors are true parallel-plate capacitors for
ultra-linear performance. Parallel-plate capacitors were chosen to reduce the
frequency shift that occurs when non-linear load capacitance interacts with load,
bias, supply, and temperature changes. External non-linear crystal load
capacitors should not be used for applications that are sensitive to absolute
frequency requirements. The value of the internal load capacitors are determined
by XTALCAP[7:0] bits, (0x07). The load capacitance can be set with a resolution
of 0.125 pF for a total crystal load range of 3.5pF to 35.4pF. Check with the
vendor's crystal load capacitance specification for the exact setting to tune the
internal load capacitor. The following equation governs how the total internal
load capacitance is set.
XTAL load cap = 3.5pF + XTALCAP[7:0] * 0.125pF (Eq. 1)
When using an external reference clock instead of a crystal on the XTAL/
REFIN pin, the input load capacitors may be completely bypassed. This allows
for the input frequency to be up to 200MHz. When using an external reference
clock, the XTALOUT pin must be left floating, XTALCAP must be programmed
to the default value of "0", and crystal drive strength bit, XDRV (0x06), must
be set to the default value of "11".
CLKIN pin is a regular clock input pin, and can be driven up to 400MHz.
Each PLL incorporates an 8-bit pre-scaler and a 12-bit feedback divider
which allows the user to generate three unique non-integer-related frequencies.
For output banks OUT2-OUT6, each bank has a 10-bit post-divider. The
following equation governs how the frequency on output banks OUT2-6 is
(Eq. 2)
Where FIN is the reference frequency, M is the total feedback-divider value,
D is the pre-scaler value, P is the total post-divider value, and FOUT is the resulting
output bank frequency. The value 2 in the denominator is due to the divide-
by-2 on each of the output banks OUT2-6. Note that OUT1 does not have any
type of post-divider. Also, programming any of the dividers may cause glitches
on the outputs.
D[7:0] are the bits used to program the pre-scaler for each PLL, D0 for
PLL0, D1 for PLL1, and D2 for PLL2. The pre-scalers divide down the
reference clock with integer values ranging from 1 to 255. To maintain low jitter,
the divided down clock must be higher than 400KHz; it is best to use the smallest
D divider value possible. If D is set to '0x00', then this will power down the PLL
and all the outputs associated with that PLL.
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The IDT5V9888 is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are three internal PLLs, each individually programmable, allowing for three unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. A glitchless automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation.
The IDT5V9888 can be programmed through the use of the I2C or JTAG interfaces. The programming interface enables the device to be pro grammed when it is in normal operation or what is commonly known as in system programmable. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. JTAG boundary scan is also implemented.
Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback divider. This allows the user to generate three unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and fractional divides are allowed on two of the PLLs.
There are 10-bit post dividers on five of the six output banks. Two of the six output banks are configurable to be LVTTL, LVPECL, or LVDS. The other four output banks are LVTTL. The outputs are connected to the PLLs via the switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each outputs slew rate and enable/disable function can be programmed.

• Three internal PLLs
• Internal non-volatile EEPROM
• JTAG and FAST mode I2C serial interfaces
• Input Frequency Ranges: 1MHz to 400MHz
• Output Frequency Ranges:
   − LVTTL: up to 200MHz
   − LVPECL/ LVDS: up to 500MHz
• Reference Crystal Input with programmable oscillator gain and
   programmable linear load capacitance
   − Crystal Frequency Range: 8MHz to 50MHz
• Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider
• 10-bit post-divider blocks
• Fractional Dividers
• Two of the PLLs support Spread Spectrum Generation capability
• I/O Standards:
   − Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS
   − Inputs - 3.3V LVTTL/ LVCMOS
• Programmable Slew Rate Control
• Programmable Loop Bandwidth Settings
• Programmable output inversion to reduce bimodal jitter
• Redundant clock inputs with glitchless auto and manual switchover options
• JTAG Boundary Scan
• Individual output enable/disable
• Power-down mode
• 3.3V VDD
• Available in TQFP and VFQFPN packages

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