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IDT5V9888 View Datasheet(PDF) - Integrated Device Technology

Part NameIDT5V9888 IDT
Integrated Device Technology IDT
Description3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
IDT5V9888 Datasheet PDF : 37 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
IDT5V9888
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Name
PF32 NL28
Pin#
Pin#
I/O
Type
Description
CLKIN
1
1
I
LVTTL
Input Clock
XTALIN/REFIN
XTALOUT
4
4
I
LVTTL
CRYSTAL_IN - Reference crystal input or external reference clock input
5
5
O
LVTTL
CRYSTAL_OUT -Reference crystal feedback
GIN0/SDAT/TDI
19
16
I
LVTTL(3)
Multi-purpose inputs. Can be used for Frequency Control, SDAT(I2C), or TDI(JTAG).
GIN1/SCLK/TCK
20
17
I
LVTTL(3)
Multi-Purpose inputs. Can be used for Frequency Control, SCLK(I2C), or TCK(JTAG).
GIN2/TMS
WRITE ENABLE
24
21
27
24
I
LVTTL(3)
Multi-Purpose inputs. Can be used for Frequency Control or TMS (JTAG).
I
LVTTL(3)
Write Enable pin. This pin must be pulled HIGH during normal operation. HIGH =
normal operation, LOW = Enable writing to internal EEPROM.
GIN3/TRST
GIN4/CLK_SEL
25
22
21
18
I
LVTTL(3)
Multi-Purpose inputs. Can be used for Frequency Control or TRST (JTAG).
I
LVTTL(3)
Multi-Purpose inputs. Can be used for Frequency Control or input clock selector.
SHUTDOWN/OE
I2C/JTAG
OUT1
28
23
I
LVTTL(3)
Enables/disables the outputs or powers down the chip. The SP bit (0x1C) controls the
polarity of the signal to be either active HIGH or LOW. (Default is active HIGH.)
22
19
I
3-level(2)
I2C (HIGH) or MFC Mode (MID) or JTAG Programming (LOW).
6
6
O
LVTTL
Configurable clock output 1. Can also be used to buffer the reference clock.
OUT2
OUT3
29
25
O
LVTTL
Configurable clock output 2
8
7
O
LVTTL
Configurable clock output 3
OUT4
OUT4
10
8
O
Adjustable(1) Configurableclockoutput4,Single-EndedorDifferentialwhencombinedwithOUT4
11
9
O
Adjustable(1) Configurable complementary clock output 4, Single-Ended or Differential when
combined with OUT4
OUT5
OUT5
15
13
O
Adjustable(1) Configurableclockoutput5,Single-EndedorDifferentialwhencombinedwithOUT5
16
14
O
Adjustable(1) Configurable complementary clock output 5, Single-Ended or Differential when
combined with OUT5
OUT6
13
11
O
LVTTL
Configurable clock output 6
GOUT0/TDO/LOSS_LOCK 31
27
O
LVTTL(3)
Multi-Purpose Output. Can be programmed to use as PLL LOCK signal, LOSS_LOCK
or TDO in JTAG mode.
GOUT1/LOSS_CLKIN
3
3
O
VDD
7,12,17, 10,15,20
23,26,32 28
LVTTL
Multi-Purpose Output. Can be programmed to use as LOSS_CLKIN.
3.3V Power Supply
GND
2,9,14, 2,12,26
18,30
Ground
NOTES:
1. Outputs are user programmable to drive single-ended 3.3V LVTTL, differential LVDS, or differential LVPECL interface levels.
2. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are internally biased to VDD/2. They are not hot-insertable or over voltage tolerant.
3. The JTAG (TDO, TMS, TCLK, TRST, and TDI) and I2C (SCLK and SDAT) signals share the same pins with GIN signals.
4
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DESCRIPTION:
The IDT5V9888 is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are three internal PLLs, each individually programmable, allowing for three unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. A glitchless automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation.
The IDT5V9888 can be programmed through the use of the I2C or JTAG interfaces. The programming interface enables the device to be pro grammed when it is in normal operation or what is commonly known as in system programmable. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. JTAG boundary scan is also implemented.
Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback divider. This allows the user to generate three unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and fractional divides are allowed on two of the PLLs.
There are 10-bit post dividers on five of the six output banks. Two of the six output banks are configurable to be LVTTL, LVPECL, or LVDS. The other four output banks are LVTTL. The outputs are connected to the PLLs via the switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each outputs slew rate and enable/disable function can be programmed.

FEATURES:
• Three internal PLLs
• Internal non-volatile EEPROM
• JTAG and FAST mode I2C serial interfaces
• Input Frequency Ranges: 1MHz to 400MHz
• Output Frequency Ranges:
   − LVTTL: up to 200MHz
   − LVPECL/ LVDS: up to 500MHz
• Reference Crystal Input with programmable oscillator gain and
   programmable linear load capacitance
   − Crystal Frequency Range: 8MHz to 50MHz
• Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider
• 10-bit post-divider blocks
• Fractional Dividers
• Two of the PLLs support Spread Spectrum Generation capability
• I/O Standards:
   − Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS
   − Inputs - 3.3V LVTTL/ LVCMOS
• Programmable Slew Rate Control
• Programmable Loop Bandwidth Settings
• Programmable output inversion to reduce bimodal jitter
• Redundant clock inputs with glitchless auto and manual switchover options
• JTAG Boundary Scan
• Individual output enable/disable
• Power-down mode
• 3.3V VDD
• Available in TQFP and VFQFPN packages

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