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IDT5V9888 View Datasheet(PDF) - Integrated Device Technology

Part NameIDT5V9888 IDT
Integrated Device Technology IDT
Description3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
IDT5V9888 Datasheet PDF : 37 Pages
First Prev 31 32 33 34 35 36 37
IDT5V9888
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
RAM (PROGRAMMING REGISTER) TABLES
BIT #
(Default Settings)
Default
ADDR 7 6 5 4 3 2 1 0 Register
7
Hex Value
BIT #
6
5
4
3
2
1
0
DESCRIPTION
0x1F 0 0 0 0 0 0 0 0
00
OEM1[1;0]
SLEW1[1:0]
INV1
Configuring Output OUT1
INV1=Output Inversion for OUT1 ("0"= Non-Invert (Default), "1"=Invert);
SLEW1=Slew Rate Settings for OUT1 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);
OEM1= Output Enable Mode for OUT1 output, when used with OE1 bit and SHUTDOWN/OE pin ("0x" = Tri-state (Default), "10"=Park
Low, "11"=Park High);
Address 0x1F, Bits 3, 1, 0 are reserved and should be set to "0"
0x20 0 0 0 0 0 0 0 0
0x21 0 0 0 0 0 0 0 0
0x22 0 0 0 0 0 0 0 0
0x23 0 0 0 0 0 0 0 0
0x24 0 0 0 0 0 0 0 0
0x25 0 0 0 0 0 0 0 0
0x26 0 0 0 0 0 0 0 0
00
ODIV1_CONFIG0
IP1[2:0]_CONFIG0
00
ODIV1_CONFIG1
IP1[2:0]_CONFIG1
00
ODIV1_CONFIG2
IP1[2:0]_CONFIG2
00
ODIV1_CONFIG3
IP1[2:0]_CONFIG3
00
CP1[3:0]_CONFIG0
00
CP1[3:0]_CONFIG1
00
CP1[3:0]_CONFIG2
RZ1[3:0]_CONFIG0
RZ1[3:0]_CONFIG1
RZ1[3:0]_CONFIG2
RZ1[3:0]_CONFIG3
CZ1[3:0]_CONFIG0
CZ1[3:0]_CONFIG1
CZ1[3:0]_CONFIG2
PLL1 LOOP FILTER SETTING
Loop Filter Values for PLL1 - For 4 Configurations (Default value is '0');
CONFIG0 will be selected if GINx are disabled and operating in MFC mode.
ODIV1_CONFIGx=Determines which one of the 2 "Qx-Divider" Configurations to use with, for any of the "Qx-Divider" block associated
with PLL1; Used in MFC mode; Default ODIV value is "0", and use CONFIG0 of Qx-Divider;
Resistor = 0.3K+ RZ1[3:0] * 1K, 0.3 to 15.3kOhm with 1kOhm Step, ("0000"=0.3kOhm, "0001"=1.3kOhm, "0010"=2.3kOhm, ...);
Zero capacitor = 6pF + CZ1[3:0] * 27.2pF, 6pF to 414pF with 27.2pF Step, ("0000"=6pF, "0001"=33.2pF, "0010"=60.4pF", ...);
Pole capacitor = 1.3pF + CP1[3:0] * 0.75pF, 1.3pF to 12.55pF with 0.75pF Step, ("0000"=1.3pF, "0001"=2.05pF, "0010"=2.8pF, ...)
Charge pump current = 5 * 2^IP1[2:0] μA, 5uA to 640uA with 5, 10, 20, 40, ... binary step;
0x27 0 0 0 0 0 0 0 0
00
0x28 0 0 0 0 0 0 0 0
00
CP1[3:0]_CONFIG3
D1[7:0]_CONFIG0
CZ1[3:0]_CONFIG3
0x29 0 0 0 0 0 0 0 0
00
0x2A 0 0 0 0 0 0 0 0
00
D1[7:0]_CONFIG1
D1[7:0]_CONFIG2
PLL1 INPUT DIVIDER D1 SETTING
PLL1 D-Divider Values (Prescaler) - For 4 Configurations (Default value is '0');
0x2B 0 0 0 0 0 0 0 0
00
D1[7:0]_CONFIG3
0x2C 0 0 0 0 0 0 0 0
00
0x2D 0 0 0 0 0 0 0 0
00
0x2E 0 0 0 0 0 0 0 0
00
0x2F 0 0 0 0 0 0 0 0
00
0x30 0 0 0 0 0 0 0 0
00
0x31 0 0 0 0 0 0 0 0
00
0x32 0 0 0 0 0 0 0 0
00
0x33 0 0 0 0 0 0 0 0
00
A1[3:0]_CONFIG0
A1[3:0]_CONFIG1
A1[3:0]_CONFIG2
A1[3:0]_CONFIG3
N1[7:0]_CONFIG0
N1[7:0]_CONFIG1
N1[7:0]_CONFIG2
N1[7:0]_CONFIG3
N1[11:8]_CONFIG0
N1[11:8]_CONFIG1
N1[11:8]_CONFIG2
N1[11:8]_CONFIG3
PLL1 MULTIPLIER SETTING
CONFIG0 will be selected if GINx are disabled and operating in MFC mode.
N1[11:0]_CONFIGx - Part of PLL1 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');
A1[3:0]_CONFIGx - Part of PLL1 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');
SSC_OFFSET1[5:0] - Spread Spectrum Fractional Multiplier Offset Value. See Spread Spectrum Settings in register address range
0x68-0x6F
Total Multiplier Value M1 = 2 * N1[11:0] + A1 + 1 + SS_OFFSET1 * 1/64
When A1[3:0] = 0 and spread spectrum disabled, M1= 2 * N1[11:0];
When A1[3:0] > 0 and spread spectrum disabled, M1 = 2 * N1[11:0] + A1 + 1 ;
(Note: A < N-1, i.e. valid M values are 2, 4, 6, 8, 9, 10, 11, 12, 13, ..., 4095 assuming within fPFD and fVCO spec);
0x34 0 1 0 0 0 1 1 0
46
0x35 0 1 0 1 0 1 0 1
55
SRC2[1:0]
SRC6[1:0]
SRC1[1:0]
SRC5[1:0]
SRC4[1:0]
SM[1:0]
PRIMCLK
PRIMCLK=Priority Selection for Input Clock ("0"=XTALIN/REF_IN becomes Primary (Default), "1"=CLK_IN becomes Primary);
SM = Switchover Mode ("0x"=Manual, "10"= Auto-NonRevertive, "11"=Auto-Revertive (Default));
Bit 3 is reserved and should be set to "0".
SRC3[1:0]
SRCx[1:0]=Input Source Selection for Output Dividers "Qx" blocks ("00"=Selected Input CLK, "01"=PLL0, "10"=PLL1, "11"=PLL2);
Default on SRC1 is the selected input clock. Default on SRC2-6 is PLL0 which will be powered down.
0x36
0x37
No Registers Exist
0x38 0 0 0 0 0 0 0 0
00
ODIV2_CONFIG0
IP2[2:0]_CONFIG0
RZ2[3:0]_CONFIG0
0x39 0 0 0 0 0 0 0 0
0x3A 0 0 0 0 0 0 0 0
0x3B 0 0 0 0 0 0 0 0
0x3C 0 0 0 0 0 0 0 0
0x3D 0 0 0 0 0 0 0 0
0x3E 0 0 0 0 0 0 0 0
00
ODIV2_CONFIG1
IP2[2:0]_CONFIG1
00
ODIV2_CONFIG2
IP2[2:0]_CONFIG2
00
ODIV2_CONFIG3
IP2[2:0]_CONFIG3
00
CP2[3:0]_CONFIG0
00
CP2[3:0]_CONFIG1
00
CP2[3:0]_CONFIG2
RZ2[3:0]_CONFIG1
RZ2[3:0]_CONFIG2
RZ2[3:0]_CONFIG3
CZ2[3:0]_CONFIG0
CZ2[3:0]_CONFIG1
CZ2[3:0]_CONFIG2
PLL2 LOOP FILTER SETTING
Loop Filter Values for PLL2 - For 4 Configurations (Default value is '0');
CONFIG0 will be selected if GINx are disabled and operating in MFC mode.
ODIV2_CONFIGx=Determines which one of the 2 "Qx-Divider" Configurations to use with, for any of the "Qx-Divider" block associated with
PLL2; Used in MFC mode; Default ODIV value is "0", and use CONFIG0 of Qx-Divider;
Resistor = 0.3K+ RZ2[3:0] * 1K, 0.3 to 15.3kOhm with 1kOhm Step, ("0000"=0.3kOhm, "0001"=1.3kOhm, "0010"=2.3kOhm, ...);
Zero capacitor = 6pF + CZ2[3:0] * 27.2pF, 6pF to 414pF with 27.2pF Step, ("0000"=6pF, "0001"=33.2pF, "0010"=60.4pF", ...);
Pole capacitor = 1.3pF + CP2[3:0] * 0.75pF, 1.3pF to 12.55pF with 0.75pF Step, ("0000"=1.3pF, "0001"=2.05pF, "0010"=2.8pF, ...)
Charge pump current = 5 * 2^IP2[2:0] μA, 5uA to 640uA with 5, 10, 20, 40, ... binary step;
0x3F 0 0 0 0 0 0 0 0
00
CP2[3:0]_CONFIG3
CZ2[3:0]_CONFIG3
33
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DESCRIPTION:
The IDT5V9888 is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are three internal PLLs, each individually programmable, allowing for three unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. A glitchless automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation.
The IDT5V9888 can be programmed through the use of the I2C or JTAG interfaces. The programming interface enables the device to be pro grammed when it is in normal operation or what is commonly known as in system programmable. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. JTAG boundary scan is also implemented.
Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback divider. This allows the user to generate three unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and fractional divides are allowed on two of the PLLs.
There are 10-bit post dividers on five of the six output banks. Two of the six output banks are configurable to be LVTTL, LVPECL, or LVDS. The other four output banks are LVTTL. The outputs are connected to the PLLs via the switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each outputs slew rate and enable/disable function can be programmed.

FEATURES:
• Three internal PLLs
• Internal non-volatile EEPROM
• JTAG and FAST mode I2C serial interfaces
• Input Frequency Ranges: 1MHz to 400MHz
• Output Frequency Ranges:
   − LVTTL: up to 200MHz
   − LVPECL/ LVDS: up to 500MHz
• Reference Crystal Input with programmable oscillator gain and
   programmable linear load capacitance
   − Crystal Frequency Range: 8MHz to 50MHz
• Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider
• 10-bit post-divider blocks
• Fractional Dividers
• Two of the PLLs support Spread Spectrum Generation capability
• I/O Standards:
   − Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS
   − Inputs - 3.3V LVTTL/ LVCMOS
• Programmable Slew Rate Control
• Programmable Loop Bandwidth Settings
• Programmable output inversion to reduce bimodal jitter
• Redundant clock inputs with glitchless auto and manual switchover options
• JTAG Boundary Scan
• Individual output enable/disable
• Power-down mode
• 3.3V VDD
• Available in TQFP and VFQFPN packages

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