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IDT5V9888 View Datasheet(PDF) - Integrated Device Technology

Part NameIDT5V9888 IDT
Integrated Device Technology IDT
Description3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
IDT5V9888 Datasheet PDF : 37 Pages
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IDT5V9888
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
AC TIMING ELECTRICAL CHARACTERISTICS
(SPREAD SPECTRUM GENERATION = OFF)
Symbol
fIN
1/t1
fVCO
fPFD
fBW
t2
t3
t4(2)
t5
t6
t7
t8
t9
t10
t11
Parameter
Input Frequency
Output Frequency
VCO Frequency
PFD Frequency
Loop Bandwidth
Input Duty Cycle
Output Duty Cycle
Slew Rate
SLEWx(bits) = 00
Slew Rate
SLEWx(bits) = 01
Slew Rate
SLEWx(bits) = 10
Slew Rate
SLEWx(bits) = 11
Rise Times
Fall Times
Rise Times
Fall Times
Output three-state Timing
Clock Jitter(3,7)
Output Skew
Lock Time
Lock time(8)
Write-Protect Time
Test Conditions
Min.
Typ.
Max
Unit
Input Frequency Limit
1(1)
400
MHz
Single Ended Clock output limit (LVTTL)
0.0049
200
MHz
Differential Clock output limit (LVPECL/ LVDS)
0.0049
500
VCO operating Frequency Range
10
1200
MHz
PFD operating Frequency Range
0.4(1)
400
MHz
Based on loop filter resistor and capacitor values
0.03
40
MHz
Duty Cycle for Input
40
60
%
Measured at VDD/2, FOUT 200MHz
45
55
%
Measured at VDD/2, FOUT > 200MHz
40
60
Single-Ended Output clock rise and fall time,
2.75
20% to 80% of VDD (Output Load = 15pf)
Single-Ended Output clock rise and fall time,
2
20% to 80% of VDD (Output Load = 15pf)
V/ns
Single-Ended Output clock rise and fall time,
1.25
20% to 80% of VDD (Output Load = 15pf)
Single-Ended Output clock rise and fall time,
0.75
20% to 80% of VDD (Output Load = 15pf)
LVDS, 20% to 80%
850
850
ps
LVPECL, 20% to 80%
500
500
Time for output to enter or leave three-state mode
150 +
ns
after SHUTDOWN/OE switches
1/FOUTX
Peak-to-peak period jitter,
fPFD > 20MHz
150
ps
CLK outputs measured at VDD/2
fPFD < 20MHz
200
Skew between output to output on the same bank
150
ps
(bank 4 and bank 5 only)(4, 5)
PLL Lock Time from Power-up(6)
10
20
ms
PLL Lock time from shutdown mode
20
100
μs
Hold Time after TSAVE for WRITE ENABLE signal
10
ms
NOTES:
1. Practical lower input frequency is determined by loop filter settings.
2. A slew rate of 2V/ns or greater should be selected for output frequencies of 100MHz and higher.
3. Input frequency is the same as the output with all output banks running at the same frequency.
4. Skew measured between all in-phase outputs in the same bank.
5. Skew measured between the cross points of all differential output pairs under identical input and output interfaces, transitions and load conditions on any one device.
6. Includes loading the configuration bits from EEPROM to PLL registers. It does not include EEPROM programming/write time.
7. Guaranteed by design but not production tested.
8. Actual PLL lock time depends on the loop configuration.
SPREAD SPECTRUM GENERATION SPECIFICATIONS
Symbol
Parameter
Description
fIN
Input Frequency
Input Frequency Limit
fMOD
Mod Freq
Modulation Frequency
fSPREAD
Spread Value
Amount of Spread Value (Programmable) - Down Spread
Amount of Spread Value (Programmable) - Center Spread
Min.
Typ.
Max
1(1)
400
33
-0.5, -1, -2.5, -3.5, -4
-0.5 to +0.5
NOTE:
1. Practical lower input frequency is determined by loop filter settings.
30
Unit
MHz
kHz
%fOUT
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DESCRIPTION:
The IDT5V9888 is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are three internal PLLs, each individually programmable, allowing for three unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. A glitchless automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation.
The IDT5V9888 can be programmed through the use of the I2C or JTAG interfaces. The programming interface enables the device to be pro grammed when it is in normal operation or what is commonly known as in system programmable. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. JTAG boundary scan is also implemented.
Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback divider. This allows the user to generate three unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and fractional divides are allowed on two of the PLLs.
There are 10-bit post dividers on five of the six output banks. Two of the six output banks are configurable to be LVTTL, LVPECL, or LVDS. The other four output banks are LVTTL. The outputs are connected to the PLLs via the switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each outputs slew rate and enable/disable function can be programmed.

FEATURES:
• Three internal PLLs
• Internal non-volatile EEPROM
• JTAG and FAST mode I2C serial interfaces
• Input Frequency Ranges: 1MHz to 400MHz
• Output Frequency Ranges:
   − LVTTL: up to 200MHz
   − LVPECL/ LVDS: up to 500MHz
• Reference Crystal Input with programmable oscillator gain and
   programmable linear load capacitance
   − Crystal Frequency Range: 8MHz to 50MHz
• Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider
• 10-bit post-divider blocks
• Fractional Dividers
• Two of the PLLs support Spread Spectrum Generation capability
• I/O Standards:
   − Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS
   − Inputs - 3.3V LVTTL/ LVCMOS
• Programmable Slew Rate Control
• Programmable Loop Bandwidth Settings
• Programmable output inversion to reduce bimodal jitter
• Redundant clock inputs with glitchless auto and manual switchover options
• JTAG Boundary Scan
• Individual output enable/disable
• Power-down mode
• 3.3V VDD
• Available in TQFP and VFQFPN packages

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