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IDT5V9888 View Datasheet(PDF) - Integrated Device Technology

Part NameDescriptionManufacturer
IDT5V9888 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR IDT
Integrated Device Technology IDT
IDT5V9888 Datasheet PDF : 37 Pages
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IDT5V9888
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
AC TIMING ELECTRICAL CHARACTERISTICS
(SPREAD SPECTRUM GENERATION = OFF)
Symbol
fIN
1/t1
fVCO
fPFD
fBW
t2
t3
t4(2)
t5
t6
t7
t8
t9
t10
t11
Parameter
Input Frequency
Output Frequency
VCO Frequency
PFD Frequency
Loop Bandwidth
Input Duty Cycle
Output Duty Cycle
Slew Rate
SLEWx(bits) = 00
Slew Rate
SLEWx(bits) = 01
Slew Rate
SLEWx(bits) = 10
Slew Rate
SLEWx(bits) = 11
Rise Times
Fall Times
Rise Times
Fall Times
Output three-state Timing
Clock Jitter(3,7)
Output Skew
Lock Time
Lock time(8)
Write-Protect Time
Test Conditions
Min.
Typ.
Max
Unit
Input Frequency Limit
1(1)
400
MHz
Single Ended Clock output limit (LVTTL)
0.0049
200
MHz
Differential Clock output limit (LVPECL/ LVDS)
0.0049
500
VCO operating Frequency Range
10
1200
MHz
PFD operating Frequency Range
0.4(1)
400
MHz
Based on loop filter resistor and capacitor values
0.03
40
MHz
Duty Cycle for Input
40
60
%
Measured at VDD/2, FOUT 200MHz
45
55
%
Measured at VDD/2, FOUT > 200MHz
40
60
Single-Ended Output clock rise and fall time,
2.75
20% to 80% of VDD (Output Load = 15pf)
Single-Ended Output clock rise and fall time,
2
20% to 80% of VDD (Output Load = 15pf)
V/ns
Single-Ended Output clock rise and fall time,
1.25
20% to 80% of VDD (Output Load = 15pf)
Single-Ended Output clock rise and fall time,
0.75
20% to 80% of VDD (Output Load = 15pf)
LVDS, 20% to 80%
850
850
ps
LVPECL, 20% to 80%
500
500
Time for output to enter or leave three-state mode
150 +
ns
after SHUTDOWN/OE switches
1/FOUTX
Peak-to-peak period jitter,
fPFD > 20MHz
150
ps
CLK outputs measured at VDD/2
fPFD < 20MHz
200
Skew between output to output on the same bank
150
ps
(bank 4 and bank 5 only)(4, 5)
PLL Lock Time from Power-up(6)
10
20
ms
PLL Lock time from shutdown mode
20
100
μs
Hold Time after TSAVE for WRITE ENABLE signal
10
ms
NOTES:
1. Practical lower input frequency is determined by loop filter settings.
2. A slew rate of 2V/ns or greater should be selected for output frequencies of 100MHz and higher.
3. Input frequency is the same as the output with all output banks running at the same frequency.
4. Skew measured between all in-phase outputs in the same bank.
5. Skew measured between the cross points of all differential output pairs under identical input and output interfaces, transitions and load conditions on any one device.
6. Includes loading the configuration bits from EEPROM to PLL registers. It does not include EEPROM programming/write time.
7. Guaranteed by design but not production tested.
8. Actual PLL lock time depends on the loop configuration.
SPREAD SPECTRUM GENERATION SPECIFICATIONS
Symbol
Parameter
Description
fIN
Input Frequency
Input Frequency Limit
fMOD
Mod Freq
Modulation Frequency
fSPREAD
Spread Value
Amount of Spread Value (Programmable) - Down Spread
Amount of Spread Value (Programmable) - Center Spread
Min.
Typ.
Max
1(1)
400
33
-0.5, -1, -2.5, -3.5, -4
-0.5 to +0.5
NOTE:
1. Practical lower input frequency is determined by loop filter settings.
30
Unit
MHz
kHz
%fOUT
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