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IDT5V9888 View Datasheet(PDF) - Integrated Device Technology

Part NameIDT5V9888 IDT
Integrated Device Technology IDT
Description3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR


IDT5V9888 Datasheet PDF : 37 Pages
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IDT5V9888
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
PROGSAVE
To save configuration into EEPROM, WRITE ENABLE pin must be set LOW
S Address R/W ACK Command Code ACK P
7-bits 0 1-bit 8-bits:xxxxxx01 1-bit
NOTE:
PROGWRITE is for writing to the 5V9888 registers.
PROGREAD is for reading the 5V9888 registers.
PROGSAVE is for saving all the contents of the 5V9888 registers to the EEPROM.
PROGRESTORE is for loading the entire EEPROM contents to the 5V9888 registers.
PROGRESTORE
S Address R/W ACK Command Code ACK P
7-bits 0 1-bit 8-bits:xxxxxx10 1-bit
JTAG INTERFACE
In addition to the IEEE 1149.1 instructions EXTEST, SAMPLE/PRELOAD,
CLAMP, HIGH-Z and BYPASS, the 5V9888 allows access to internal
programming registers using the REGADDR (set register address), REGDATAR
(read register) and REGDATW (write register instructions. Data is always
accessed by byte, and the register address increments after each read or write.
The full instruction set follows. The IDT5V9888 will be updating the registers
during programming.
The JTAG TAP controller can be reset in one of four ways:
1) Power up in JTAG mode
2) PowerupinI2CmodeandthengointoJTAGmode,orgooutofandback
into JTAG mode with the I2C/JTAG pin
3) Apply TRST while in JTAG mode
4) Apply five rising edges of TCK with TMS high while in JTAG mode
JTAG INSTRUCTION REGISTER
DESCRIPTION
IR (3)
0
0
0
0
0
0
0
0
1
1
1
IR (2)
0
0
0
0
1
1
1
1
0
0
1
IR (1)
0
0
1
1
0
0
1
1
0
0
1
IR (0)
0
1
0
1
0
1
0
1
0
1
1
Instructions
EXTEST(1)
SAMPLE/PRELOAD(1)
IDCODE(1)
REGADDR(2)
REGDATAW / PROGWRITE(3)
REGDATAR / PROGREAD(4)
PROGSAVE(5)
PROGRESTORE(6)
CLAMP(1)
HIGHZ(1,7)
BYPASS(1)
NOTES:
1. IEEE 1149.1 definition
2. REGADDR is for setting a specific 5V9888 register address.
3. REGDATAW/PROGWRITE is for writing to the 5V9888 registers.
4. REGDATAR/PROGREAD is for reading the 5V9888 registers.
5. PROGSAVE is for saving all the contents of the 5V9888 registers to the EEPROM.
WRITE ENABLE pin must be asserted LOW.
6. PROGRESTORE is for loading the entire EEPROM contents to the 5V9888 registers.
7. The OEMs bits for OUT1-6 must be set for tri-state when using the HIGHZ instruction
EEPROM INTERFACE
The IDT5V9888 can also store its configuration in an internal EEPROM. The contents of the device's internal programming registers can be saved to the
EEPROM by issuing a save instruction (ProgSave) and asserting the WRITE ENABLE pin LOW. They can be loaded back to the internal programming registers
by issuing a restore instruction (ProgRestore).
To initiate a save or restore using I2C, only two bytes are transferred. The Device Address is issued with the read/write bit set to "0", followed by the appropriate
command code. The save or restore instruction executes after the STOP condition is issued by the Master, during which time the IDT5V9888 will not generate
Acknowledge bits. The 5V9888 will acknowledge the instructions after it has completed execution of them. During that time, the I2C bus should be interpreted
as busy by all other users of the bus.
Using JTAG, the ProgSave and ProgRestore instructions selects the BYPASS register path for shifting the data from TDI to TDO during the data register scanning.
During the execution of a ProgSave or ProgRestore instruction, the IDT5V9888 will not accept a new programming instruction (read, write, save, or restore).
All non-programming JTAG instructions will function properly, but the user should wait until the save or restore is complete before issuing a new programming
instruction. If a new programming instruction is issued before the save or restore completes, the new instruction is ignored, and the BYPASS register path remains
in effect for shifting data from TDI to TDO during data register scanning.
The time it takes for the save (TSAVE) and restore (TRESTORE) instructions to complete is:
TSAVE = 100ms max, TRESTORE = 10 ms max
WRITE ENABLE should stay low for at least 10ms after the completion of a save instruction.
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DESCRIPTION:
The IDT5V9888 is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are three internal PLLs, each individually programmable, allowing for three unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. A glitchless automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation.
The IDT5V9888 can be programmed through the use of the I2C or JTAG interfaces. The programming interface enables the device to be pro grammed when it is in normal operation or what is commonly known as in system programmable. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. JTAG boundary scan is also implemented.
Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback divider. This allows the user to generate three unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and fractional divides are allowed on two of the PLLs.
There are 10-bit post dividers on five of the six output banks. Two of the six output banks are configurable to be LVTTL, LVPECL, or LVDS. The other four output banks are LVTTL. The outputs are connected to the PLLs via the switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each outputs slew rate and enable/disable function can be programmed.

FEATURES:
• Three internal PLLs
• Internal non-volatile EEPROM
• JTAG and FAST mode I2C serial interfaces
• Input Frequency Ranges: 1MHz to 400MHz
• Output Frequency Ranges:
   − LVTTL: up to 200MHz
   − LVPECL/ LVDS: up to 500MHz
• Reference Crystal Input with programmable oscillator gain and
   programmable linear load capacitance
   − Crystal Frequency Range: 8MHz to 50MHz
• Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider
• 10-bit post-divider blocks
• Fractional Dividers
• Two of the PLLs support Spread Spectrum Generation capability
• I/O Standards:
   − Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS
   − Inputs - 3.3V LVTTL/ LVCMOS
• Programmable Slew Rate Control
• Programmable Loop Bandwidth Settings
• Programmable output inversion to reduce bimodal jitter
• Redundant clock inputs with glitchless auto and manual switchover options
• JTAG Boundary Scan
• Individual output enable/disable
• Power-down mode
• 3.3V VDD
• Available in TQFP and VFQFPN packages

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