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IDT5V9888 View Datasheet(PDF) - Integrated Device Technology

Part NameDescriptionManufacturer
IDT5V9888 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR IDT
Integrated Device Technology IDT
IDT5V9888 Datasheet PDF : 37 Pages
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IDT5V9888
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
EXTERNAL I2C INTERFACE CONDITION
KEY:
INDUSTRIAL TEMPERATURE RANGE
From Master to Slave
111222333444 From Master to Slave, but can be omitted if followed by the correct sequence
Normally data transfer is terminated by a STOP condition generated by the Master. However, if the Master still wishes to communicate on the bus, it can
generate a repeated START condition, and address another Slave address without first generating a STOP condition.
From Slave to Master
SYMBOLS:
ACK - Acknowledge (SDA LOW)
NACK - Not Acknowledge (SDA HIGH)
Sr - Repeated Start Condition
S - START Condition
P - STOP Condition
PROGWRITE
S Address R/W ACK Command Code ACK Register ACK Data ACK P
7-bits 0 1-bit 8-bits: xxxxxx00 1-bit 8-bits 1-bit 8-bits 1-bit
Figure 3: Progwrite Command Frame
Writes can continue as long as a Stop condition is not sent and each byte will increment the register address.
PROGREAD
Note: If the expected read command is not from the next higher register to the previous read or write command, then set a known "read" register address
prior to a read operation by issuing the following command:
S Address R/W ACK Command Code ACK Register ACK P
7-bits 0 1-bit 8-bits: xxxxxx00 1-bit 8-bits 1-bit
Figure 4a: Prior to Progread Command Set Register Address
The user can ignore the STOP condition above and use a repeated START condition instead, straight after the slave acknowledgement bit (i.e., followed by
the Progread command):
Sr Address R/W ACK ID Byte ACK Data_1 ACK Data_2 ACK Data_last NACK P
7-bits 1 1-bit 8 bits 1-bit 8-bits 1-bit 8-bits 1-bit 8-bits 1-bit
Figure 4b: Progread Command Frame
Note: Figure 4b above by itself is the Progread command format. The ID byte for the 5V9888 is 10hex. Each byte recieved increments the register address.
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