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IDT5V9888 View Datasheet(PDF) - Integrated Device Technology

Part NameIDT5V9888 IDT
Integrated Device Technology IDT
Description3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
IDT5V9888 Datasheet PDF : 37 Pages
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IDT5V9888
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
MANUAL FREQUENCY CONTROL (MFC) BLOCK DIAGRAM
PLL0
Prescaler "D"
CONFIG0
CONFIG1
CONFIG2
CONFIG3
VCO
Multiplier "M"
CONFIG0
CONFIG1
CONFIG2
CONFIG3
ODIV
ODIV
ODIV
ODIV
OUTPUT MUX
Output Divider P2
CONFIG0
CONFIG1
ODIV
Output Divider P3
CONFIG0
CONFIG1
PLL1
Prescaler "D"
CONFIG0
CONFIG4
CONFIG5
VCO
Multiplier "M"
CONFIG0
ODIV
CONFIG4
CONFIG5
ODIV
ODIV
ODIV
PLL2
Prescaler "D"
CONFIG0
CONFIG6
CONFIG7
VCO
Multiplier "M"
CONFIG0
ODIV
CONFIG6
CONFIG7
ODIV
ODIV
MFC = 1
NOTES:
This illustration shows how the configurations are arranged for PLL0. Config_4 and Config_5 are taken from PLL1, and Config_6 and Config_7 are taken from PLL2. There is an
ODIV bit associated with each of the four configurations.
- GIN0, GIN1, and GIN2 control eight shaded configurations for PLL0.
- ODIV from each configuration determines the selection of two Output Divider Px Configurations.
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DESCRIPTION:
The IDT5V9888 is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are three internal PLLs, each individually programmable, allowing for three unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. A glitchless automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation.
The IDT5V9888 can be programmed through the use of the I2C or JTAG interfaces. The programming interface enables the device to be pro grammed when it is in normal operation or what is commonly known as in system programmable. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. JTAG boundary scan is also implemented.
Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback divider. This allows the user to generate three unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and fractional divides are allowed on two of the PLLs.
There are 10-bit post dividers on five of the six output banks. Two of the six output banks are configurable to be LVTTL, LVPECL, or LVDS. The other four output banks are LVTTL. The outputs are connected to the PLLs via the switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each outputs slew rate and enable/disable function can be programmed.

FEATURES:
• Three internal PLLs
• Internal non-volatile EEPROM
• JTAG and FAST mode I2C serial interfaces
• Input Frequency Ranges: 1MHz to 400MHz
• Output Frequency Ranges:
   − LVTTL: up to 200MHz
   − LVPECL/ LVDS: up to 500MHz
• Reference Crystal Input with programmable oscillator gain and
   programmable linear load capacitance
   − Crystal Frequency Range: 8MHz to 50MHz
• Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider
• 10-bit post-divider blocks
• Fractional Dividers
• Two of the PLLs support Spread Spectrum Generation capability
• I/O Standards:
   − Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS
   − Inputs - 3.3V LVTTL/ LVCMOS
• Programmable Slew Rate Control
• Programmable Loop Bandwidth Settings
• Programmable output inversion to reduce bimodal jitter
• Redundant clock inputs with glitchless auto and manual switchover options
• JTAG Boundary Scan
• Individual output enable/disable
• Power-down mode
• 3.3V VDD
• Available in TQFP and VFQFPN packages

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