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IDT5V9888 View Datasheet(PDF) - Integrated Device Technology

Part NameIDT5V9888 IDT
Integrated Device Technology IDT
Description3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR


IDT5V9888 Datasheet PDF : 37 Pages
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IDT5V9888
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
CONFIGURING THE MULTI-PURPOSE I/Os
The 5V9888 can operate in four distinct modes. These modes are controlled by the MFC bit (0x04) and the I2C/JTAG pin. The general purpose I/O pins
(GIN0, GIN1, GIN2, GIN3, GIN4) have different uses depending on the mode of operation. The four available modes of operation are:
1) Manual Frequency Control (MFC) Mode for PLL0 Only
2) Manual Frequency Control (MFC) Mode for all three PLLs
3) I2C Programming Mode
4) JTAG Programming Mode
Along with the GINx pins are also GOUTx output pins that can take up a different function depending on the mode of operation. See table below for description.
Multi-Purpose Pins
GIN0
GIN1
GIN2
GIN3
GIN4
GOUT0
GOUT1
Other Signal Functions
SDAT / TDI
SCLK / TCK
TMS
TRST
CLK_SEL
TDO / LOSS_LOCK
LOSS_CLKIN
Signal Description
I2C serial data input / JTAG serial data input
I2C clock input / JTAG clock input
JTAG control signal to the TAP controller state machine
JTAG active LOW input to asynchronously reset the BST
Reference clock select between XTALIN/REFIN and CLKIN
JTAG serial data output / Detects loss of PLL lock(1)
Detects loss of the selected clock source(1)
NOTE:
1. LOSS_LOCK and LOSS_CLKIN cannot be used as reliable inputs to other devices.
Each PLL's programming registers can store up to four different Dx and Mx configurations in combination with two different P configurations in MFC modes.
The post-divider should never be disabled in any of the two P configurations unless the output bank will never be used during normal operation. The PLL's
loop filter settings also has four different configurations to store and select from. This will be explained in the MODE1 and MODE2 sections. The use of the GINx
pins in MFC mode control the selection of these configurations.
MODE1 - Manual Frequency Control (MFC) Mode for PLL0 Only
In this mode, only the configuration of PLL0 can be changed during operation.. PLL1 and PLL2 have only one fixed configuration in this mode. The GIN0,
GIN1 and GIN2 pins control the selection of up to eight different D0, M0, P, RZ0, CZ0, PZ0, and IP0 stored configurations. GIN3 is not available to users and
GIN4 becomes CLK_SEL pin. The output GOUT0 will become an indicator for loss of PLL lock (LOSS_LOCK).
GOUT1 pin will become an indicator for loss of the selected clock (LOSS_CLKIN).
PLL0 itself only has four different configurations to choose from but in this mode, it borrows two configurations (Config2 and Config3) from both PLL1 and PLL2,
to provide eight different stored configurations. PLL1 and PLL2 will still be fully operational but the default configuration will be Config0. The output banks will
each have two P configurations that can be associated with each of the PLL configurations. Each of the two P configurations has its own set of PM bits (See the
PRE-SCALERS, FEEDBACK-DIVIDERS, POST-DIVIDERS section for more detail on the PM bits). Use the ODIV bit to choose which post-divider configuration
to associate with a specific PLL configuration. For example, if ODIV0_CONFIG0=1, then when Config0 is selected Qx[9:0]_CONFIG1 is selected as the post-
divider value to be used. Or if ODIV2_CONFIG3 = 0, then when CONFIG7 is selected, Qx[9:0]_CONFIG0 is selected. Note that there is an ODIVx bit for each
of the PLL configurations. In this way, the post-divider values can change with the configuration.
To enter this mode, users must set MFC bit to "1", and I2C/JTAG pin must be left floating.
GIN2 Pin
0
0
0
0
1
1
1
1
GIN1 Pin
0
0
1
1
0
0
1
1
GIN0 Pin
0
1
0
1
0
1
0
1
PLL0 Configuration Selection (Mode 1)
Configuration 0: D0_CONFIG0, M0_CONFIG0, and ODIV0_CONFIG0
Configuration 1: D0_CONFIG1, M0_CONFIG1, and ODIV0_CONFIG1
Configuration 2: D0_CONFIG2, M0_CONFIG2, and ODIV0_CONFIG2
Configuration 3: D0_CONFIG3, M0_CONFIG3, and ODIV0_CONFIG3
Configuration 4: D1_CONFIG2, M1_CONFIG2, and ODIV1_CONFIG2
Configuration 5: D1_CONFIG3, M1_CONFIG3, and ODIV1_CONFIG3
Configuration 6: D2_CONFIG2, M2_CONFIG2, and ODIV2_CONFIG2
Configuration 7: D2_CONFIG3, M2_CONFIG3, and ODIV2_CONFIG3
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DESCRIPTION:
The IDT5V9888 is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are three internal PLLs, each individually programmable, allowing for three unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. A glitchless automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation.
The IDT5V9888 can be programmed through the use of the I2C or JTAG interfaces. The programming interface enables the device to be pro grammed when it is in normal operation or what is commonly known as in system programmable. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. JTAG boundary scan is also implemented.
Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback divider. This allows the user to generate three unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and fractional divides are allowed on two of the PLLs.
There are 10-bit post dividers on five of the six output banks. Two of the six output banks are configurable to be LVTTL, LVPECL, or LVDS. The other four output banks are LVTTL. The outputs are connected to the PLLs via the switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each outputs slew rate and enable/disable function can be programmed.

FEATURES:
• Three internal PLLs
• Internal non-volatile EEPROM
• JTAG and FAST mode I2C serial interfaces
• Input Frequency Ranges: 1MHz to 400MHz
• Output Frequency Ranges:
   − LVTTL: up to 200MHz
   − LVPECL/ LVDS: up to 500MHz
• Reference Crystal Input with programmable oscillator gain and
   programmable linear load capacitance
   − Crystal Frequency Range: 8MHz to 50MHz
• Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider
• 10-bit post-divider blocks
• Fractional Dividers
• Two of the PLLs support Spread Spectrum Generation capability
• I/O Standards:
   − Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS
   − Inputs - 3.3V LVTTL/ LVCMOS
• Programmable Slew Rate Control
• Programmable Loop Bandwidth Settings
• Programmable output inversion to reduce bimodal jitter
• Redundant clock inputs with glitchless auto and manual switchover options
• JTAG Boundary Scan
• Individual output enable/disable
• Power-down mode
• 3.3V VDD
• Available in TQFP and VFQFPN packages

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