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IDT5V9888 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR IDT
Integrated Device Technology IDT
IDT5V9888 Datasheet PDF : 37 Pages
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IDT5V9888
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
To determine if the loop is stable, the phase margin (ωm) would need to be calculated as follows.
Phase Margin:
ωz = 1 / (Rz * Cz)
ωp = Cz + Cp
Rz * Cz * Cp
(Eq. 23)
(Eq. 24)
φm = (360 / 2π ) * [tan-1(ωc/ ωz) - tan-1(ωc/ ωp)]
(Eq. 25)
To ensure stability in the loop, the phase margin is recommended to be > 60° but too high will result in the lock time being excessively long. Certain loop filter
parameters would need to be compromised to not only meet a required loop bandwidth but to also maintain loop stability.
Example
Fc = 150KHz is the desired loop bandwidth. The total M value is 850. The ratio of ωp/ωc should be at least 4. A rule of thumb that will help to aid the way,
the ωp / ωc ratio should be at least 4. Given Fc and M, an optimal loop filter setting needs to be solved for that will meet both the PLL loop bandwidth and maintain
loop stability.
The charge pump gain should be relatively small as possible to achieve a low loop bandwidth.
Ip = 40uA .
Kφ * KVCO = 950MHz/V * 40uA = 38000A/Vs
Loop Bandwidths
ωc = 2π * Fc = 9.42x105 s-1
ωuz = ωp / ωc = 4
(Eq. 26)
ωc2 = ωp * ωz
(Eq. 27)
ωp = Cz + Cp = ωz (1 + Cz / Cp)
Rz * Cz * Cp
Solving for Cz, Cp, and Rz
Knowing ωc = Rz * Kφ * KVCO * Cz and substituting in the equations from above,
M * (Cz + Cp)
Cz >>> Cp, therefore, we can easily derive Cp to be
Cp = Kφ * KVCO = 12.60pF
M * ωc2 * ωuz
Similarly for Cz and Rz
Cz = Kφ * KVCO * (ωuz2 - 1) = Cp * (ωuz2 - 1) = 189pF
M * ωc2 * ωuz
Rz = M * ωc * ωuz2 = 22.48KΩ
Kφ * KVCO * (ωuz2 - 1)
Based on the loop filter parameter equations from above, since there are no possible values of 12.60pF for Cp, 189pF for Cz, and 22.48KΩ for Rz, the next
possible values within the loop filter settings are 12.55pF (CP[3:0]=1111), 196.4pF (CZ[3:0]=0111), and 15.3KΩ (RZ[3:0]=1111), respectively. This loop filter
setting will yield a loop bandwidth of about 102KHz. The phase margin must be checked for loop stability.
φm = (360 / 2π ) * [tan-1 (6.41x105 s-1 / 3.33x105 s-1) - tan-1 (6.41x105 s-1 / 5.54x106 s-1)] = 56°
Although slightly below 60°, the phase margin would be acceptable with a fairly stable loop.
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